Xilinx 2.5D FPGAs
Liam Madden, corporate VP of Xilinx, gave the keynote presentation to kick off the 2011 IMAPS 44th Int. Symp. on Microelectronics a few weeks ago in Long Beach CA.
Last fall Xilinx announced a single layer, multi chip silicon interposer for its 28nm 7 series FPGAs. Looking at module assembly, first the four 28nm chiplets are mounted on a 25 × 31 mm , 100μm thick, silicon interposer with 45μm pitch microbumps and 10μm TSV. The interposer is then assembled on a 35 × 35mm BGA with 180μm pitch C4 bumps. The FPGA slices are connected by ~10,000 connections created on the silicon interposer. Compared to connections on a PWB, the interposer interconnect technology provides over 100× the die-to-die connectivity bandwidth per watt, at one-fifth the latency.
Madden indicated that the use of an interposer (known as 2.5D) was the right choice for FPGAs since the "10,000 routing connections" if they would have been TSV in the FPGA slices, would have used up valuable chip area making the chips larger and more costly than they are now.
TSMC is fabricating the chip and the interposer and bumping the interposer, while Amkor is bumping the chip and doing the module assembly. Madden gladly showed one of the modules to the packed audience:
[Madden showing Virtex 7 module with James Lu ( RPI) and GS Kim (CEO of EPworks) looking on]
Madden indicated that the Virtex 7 HT will consist of 3 FPGA slices and two 28gbps SerDes chips on an interposer capable of operating at 2.8Tb/sec. In their paper "Advanced Thermal study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA," Xilinx details the thermal study of TSV interposer technology for high performance 28nm logic die mounted on a silicon interposer with Cu-filled TSV. Based on DOE experimental results optimized TIM material, underfill, bump pitch and passive heat sinks were selected resulting in the following optimized thermal results at 55°C or 75°C ambient. Simulation results confirm that for the selected passive heat sink the high power FPGA package is thermally reliable and meets thermal specs.
Xilinx also reported on quality and reliability in their paper "Quality and Reliability of 3D Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology." Microbump (FPGA to interposer) resistance was measured from Kelvin structure measurements.
Interposer stress and delamination risk were carefully studied through simulation and thermal cycling. Simulation results indicated that the overall stresses in the silicon, SiO2 insulator and copper via are below the fracture strength of the given materials.
During package level reliability testing, the 3 main factors evaluated were type of underfill, top die thickness and interposer cleaning . Test samples were exposed to level 5 preconditioning, HTOL (high temp operating life) and TC (temp cycling). Reliability results showed that higher Tg underfills passed all tests . Failures were observed with lower Tg underfills. In addition proper interposer cleaning and die thickness reduction were necessary to prevent delamination.
Wafer applied underfills for 3D
IMEC addressed the "Use of Wafer Applied Underfill for 3D Stacking." In the case of die-to-package UF one is looking to mitigate the CYE differences between the laminate package substrate, the ~100μm solder bumps, the silicon die, and the package overmolding -- whereas in the case of die to die assembly such as 3D structures the underfill has to mitigate the CTE differences between the 2 silicon die and the ~ 10μm microbumps. Thus there are different requirements for the two.
In 3D packaging the main challenges for underfill are the narrow gaps between the chips and/or the chip and the substrate (~10μm) and the fine pitch between the bumps (i.e. 20μm). The use of capillary underfill (CUF) is time-consuming as requires excess space around the die for the dispense action. In the case of no flow underfill (NUF) the materials is dispensed on the substrate before the die stacking. Materials need to be transparent so you can see the alignment marks during the flip chip operation, dispense timing since this is still done for each individual die and underfill/filler entrapment between the bump and the pad.
For 3D, CUF is not an option due to the narrow gap and the fine bump pitch. NUF is a better choice but suffers from the transparency requirement and dispense volume control (i.e. excess underfill can be thicker than the bumps and thus hinder chip to chip bonding and/or squeezing out excess underfill can "backside overflow" (see pic below) which can contaminate backside pads.
Wafer applied underfill is considered a strong candidate for 3D because theoretically it can significantly increase throughput. It can be done by either spin coating or dry film lamination.
IMEC challenged 9 global underfill suppliers with the following criteria:
- Uniform material thickness ( < 30μm, target 10μm)
- Gap fill for <40μm bump pitch
- Transparent to allow alignment
- Tacky at ambient temp
- Low cure temp, usable up to 250°C
One spin coat and two dry film materials were submitted for testing. After initial testing IMEC was left with one spin on material and two dry films.
After fabrication of test vehicles IMEC daisy chain yields of 0% eliminated the "hybrid dry film" and resulted in 20%-50% yields for the remaining epoxy spin on and dry film. The latter two materials are being considered for further development.
3D activity at ITRI
John Lau and co-workers from ITRI gave several presentations on the various aspects of 3D IC that they are working on at ITRI, many of them tied to their 3DIC test vehicle. [ see IFTLE 52, "3D and Adv Pkging at ICEP 2011"]
In their paper "Oxide Liner, Barrier and Seed Layers and Cu Plating of Blind TSVs on 300 mm Wafers for 3D IC Integration" they focused on their process development for TSV filling. They use an AMAT PECVD to deposit TEOS SiO2. At 180°C deposition temperature they find that step coverage is improved by higher temp, higher Rf power, lower pressure, and lower TEOS flow.
For barrier layer and seed, a AMAT self ionized plasma PVD system is used for Ta barrier and Cu seed. They achieved < 50 pA leakage current between 10μm × 60μm TSV. In their paper "Thin Wafer Handling of 300mm Wafers for 3D IC Integration" IRTI points out that if your dicing tape adhesive strength is "too strong" it may strip immersion gold off of the chip pads. In their presentation "Wafer bumping and Characterization of Fine Pitch Lead Free Solder Micro bumps on 300mm wafers for 3DIC integration" they offer that the difference in volume between FC solder balls and micro bumps is > 20× and the smaller and thus IMC and Kirkendall void formation issues are more pronounced for the smaller bumps. For this reason ITRI does not reflow the micro bumps before joining and the micro bump assembly is usually fluxless to reduce the chance of entrapping flux during solder reflow. Underfills are more critical for micro bumps. UBM thickness is > 10× less and the budget for undercutting the micro bumps is much smaller meaning that the process windows are smaller.
For all the latest on 3D IC and advanced packaging stay linked to IFTLE..........
We have previously reported that the IEEE International 3DIC Conference was moved from its initial October 2011 date outside Tokyo to Jan 31st 2012 in Osaka due to the unfortunate earthquake/tsunami events of this past year. The US program committee, which was scheduled to hold the 2012 even in San Francisco in October 2012, has decided to postpone their event till 2013 in deference to the unusual events surrounding the 2011 Japan meeting. We strongly recommend support of the coming meeting in Osaka.