Sunday, February 16, 2014
Thursday, February 6, 2014
Thursday, January 16, 2014
IFTLE 177 Monolithic 3DIC ; Merck acquires AZEM; Intel Invests in SBA Materials; Xilinx Wins Semi Award
Will these advances allow monolithic 3DIC to compete with TSV based 3DIC ? Some say that sequential 3D technology can be much less complex and expensive to implement,...maybe we will be finding out soon.
2013 Semi Award to Xilinx
SEMI has announced that Xilinx is a recipient of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer “which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging” Liam Madden accepted the award on behalf of the Xilinx which includes Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young.
Semi stated that “Xilinx use of a silicon interposer in their packaging of advanced FPGA represents a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die…. While the elements of redistribution layers on silicon, TSVs, and microbumps were already available [they had not been combined commercially] to provide this high bandwidth, low power packaging solution.”
For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………….
Wednesday, January 15, 2014
Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.
Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60 GHz system in US is from 57-64 GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300 μm
Aoki of Hitachi and collegues at ASET described activities on IC stacking using vias last / backside. Compared with the “via-middle”, the “backside-via-last TSV” can reduce process cost
Koyanagi’s group at Tohoku Univ reported on “Reliability Issues Related to TSVs”
It is known that a compressive stress is induced in the Si substrate next to Cu-TSV. Mechanical stresses decrease as the TSV size decreases whereas they increase as the TSV spacing decreases.
Cu Pop-up from TSVs
It is very important in order to suppress Cu diffusion from TSVs that a barrier metal layer is uniformly formed with a high step-coverage within Si trenches before Cu electroplating for Cu-TSV formation. Step-coverage of barrier metal depends on the size and aspect ratio of Si trench.
Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient.
Reliability Issues in Thinned Wafer
Saturday, January 4, 2014