Unlike a few years ago where Universities were the main groups involved with developing 3D test protocols, the 3D Test workshop list of corporate sponsors now says all we need to say about the desire for the world's major design and test houses being involved.
Eric Strid of Cascade Microtech looked at the status of probing:
Brandon Noia and Krishnendu Chakrabarty of Duke University looked at "Methodology for Pre-bond Test of TSVs and Breakpoints in High Performance 3D-SICs." If we assume the following is the accepted 3D Manufacturing/Test flow:
The goal is to detect TSV defects prior to bonding (pre-bond) but we are faced with:
-- Pre-bond TSVs are single ended
-- Current probe technology: Minimum pitch 35μm but TSVs will be ≤5μm with pitch of ≤10μm and densities of ≥10,000/mm2
TSV test can be done by BIST (built-in self test) and DfT (design for test).
In a joint presentation between Cadence, IMEC and TSMC entitled Automation of DfT Insertion and Interconnect Test Generation for 3D Stacked ICs", Sergej Deutsch of Cadence concluded:
- 3D test challenges include pre-bond and post-bond testing
- 3D-DfT architecture
-- I/O wrap and test-only pads for pre-bond testing
-- Serial and parallel test access mechanisms
-- Test turns: to bypass upper dies in stack
-- Test elevator mode: for test paths to/from upper dies
-- DRAM top control interface
- 3D wrapper insertion flow
-- Inserts 1500-style wrappers and 1149.1 for bottom die
-- Includes controls for I/O wrap and DRAM testing
-- Generates input to run ATPG
- Industrial case study concludes: negligible area costs of 3D wrapper
Etienne Racine of Mentor Graphics gave a look at TSMC's RF12 reference flow for die stacked on interposer.
For wide IO DRAM they offer the following:
Larry Smith from SEMATECH's Standards group discussed the 3D Enablement Center, which was announced December 2010 by SEMATECH, SIA, and SRC. It is designed to meet SIA member needs in high performance, mobile, analog, mixed signal, MEMS, fabless, fablite, IDMs. Their mission: "Enable industry-wide ecosystem readiness for cost effective TSV-based 3D stacked IC solutions." Members include: ASE, Altera, ADI, LSI, NIST, ON Semi, Qualcomm, Hynix, CNSE, GlobalFoundries, Hewlett Packard, IBM, Intel, Samsung, TSMC, and UMC. Initial focus is on wide IO DRAM for mobile and high-performance applications:
Erik Jan Marinissen of IMEC updated the group on the status of IEEE P1838 the “3D-Test Standardization Study Group” chartered with defining the standards in 3D test and DfT. Their current project is P1838: “Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits”.
-- Generic test access to and between dies in a multi-die stack
-- Prime focus on stacks with TSV-based interconnects
-- Pre-bond, mid-bond (partial stack), post-bond (complete stack)
-- Intra-die circuitry and inter-die interconnects
-- Pre-packaging, post-packaging, board-level situations
-- Die-level features comprise a stack-level architecture
-- Compliance to standard pertains to a die (not to the stack)
-- Enables interoperability between die and stack maker(s)
-- Standard does not address stack/product-level challenges/solutions (e.g. boundary scan for board-level interconnect testing)
-- However, standard should not prohibit application thereof
Two standardized components:
-- 3D test wrapper hardware per die
-- Description + description language
-- Based on and works with digital scan-based test access
Leverage existing DfT wherever applicable/appropriate:
-- Test access ports (such as IEEE 1149.x)
-- On-die design-for-test (such as IEEE 1500)
-- On-die design-for-debug (such as IEEE P1687)
Standard does not mandate:
-- Specific defect or fault models
-- Test generation methods
-- Die-internal design-for-test
Further info can be obtained here: 3D-Test WG or here: Project P1838.
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