Sunday, February 16, 2014

IFTLE 180 GaTech Interposer Conf ; Glass and Organic Interposers

Continuing our look at the 2013 GaTech Interposer Conference.


A reader has written in to indicating that the FPGA chip described in the Xilinx/SPIL paper was fabricated by TSMC not UMC .

Corning and Schott Glass

As discussed in IFTLE 170, Windsor Thomas of Corning gave a presentation entitled “The manufacturing readiness of Glass interposers” and Schott glass followed with a presentation entitled “New Ultra-thin Glass for Microelectronics”.

Since the whole LCD infrastructure is based on thin glass we certainly did not need any convincing that large panel, uniform, thin glass is available in roll and/or large panel format. Corning like Asahi Glass and Schott glass has been researching the formation of TSV (or TGV) for several years now and all appear somewhat able to form through vias down to maybe 25um. The real question is how do we than use this feedstock to get low cost glass interposers.

Though we were shown some Cu fill experiments, neither Corning nor Schott  indicated that they would enter the interposer market, did not indicate who such a partner would be and in fact stated that their discussions with the FPD industry( which they most certainly now supply) indicate that there is absolutely no interest in FPD suppliers entering the interposer supply market.  

IFTLE concludes that if any of the current glass suppliers want to see glass become a interposer substrate material and more broadly a preferred packaging substrate material, they must resolve who will actually be supplying the final packaging products.

Asahi glass has attempted to fill this void with Triton, their JV with nMode [see IFTLE 141,“100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory” ] Corning and Schott have not yet indicated what their proposed solutions are.


Koizumi-san  of Shinko discussed glass substrate prototyping status. Shinko points out that glass cores can be used to mimic Si like interposers or build-up PCB substrates.
He showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core. Modeling calculations show that the glass internal stress is mainly caused by the total copper layer thickness.

John Xie of Altera examined the use of organic interconnect for stacked die integration.  Altera’s take on Interconnect resolution trends are compared below. The proposal is that organic build up (BU) substrate (dry processed) is rapidly approaching the capabilities of this film BE of line packaging on silicon.
Xie contends that high end substrate suppliers are quickly approaching 2/2 L/S and will allow direct attach to substrate and elimination of the interposer as shown below. This in turn will be a cost reduction driver. He calls this 2.1D or Ultra high density organic  interconnect. They can currently get 92um bump pitch, 8um lines and 80um vias. Their 2 year goal is to obtain 55um bump pitch, 2um lines and 20um vias.


Zeon introduced their ultra tine dry films for Interposer RDL applications. Properties of the Zeon “cyclo olefin” polymer film are shown below.

Ushio addressed large area litho tools for 1 – 5µm  L/S. They claim their tool is capable of 2µm L/S in a 70 x 70 sq mm area.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE………….

IFTLE 179 GaTech Interposer Conf; Amkor, GlobalFoundries

Continuing our look at the 2013 GaTech Interposer Conference.


Ron Huemoeller of Amkor addressed interposer use, defining the markets and materials options as follows:


Amkor projects that in the high end silicon will dominate; in the mid end silicon will be prominent and organic /glass may play a role; in the low end organic, or low cost glass or silicon if they exist will play a role.
Silicon Interposers
Product Applications
- Gaming, HDTV, mobile tablets, computing, servers
- High end graphics cards will be the initial focus of HBM memory integration
- mobile space has the potential to follow based on availability of low cost solutions
Visible and Anticipated Demand
- continued low volume production of FPGAs and ASICs
- moderate volumes for high end graphics cards; HBM cost/availability driven
- high volumes for mobile; interposer cost driven at less than $0.01 per sq mm.
 Market Longevity
- expect to have a very long life cycle
- long term continued use through deconstruction of very high end node logic to address system level cost and power related memory integration issues.
Amkor describes the silicon interposer supply chain
-  Current
- TSMC – not supplying to the industry
- UMC and Global Foundries – both have limited capacity and neither desires to be a merchant supplier
- Future
- Yet unannounced merchant supplier
- use of depreciated equipment and excess capacity
- lowers cost vs tier 1 foundries
- supply interposer without desire to bundle chip fab.
Organic Interposer Sources:
- Tier 1 Shinko, SEMCO
              - 2/2 (L/S) 10/22 (via/pad); very limited sampling
- Tier 2 Kyocera
               - 5/5 (L/S); 18/30 (vias/pads); very limited sampling
- Tier 3 Kinsus, Unimicron
              - early development
Dave McCann of GlobalFoundries examined market needs for interposers. McCann used the latest Gartner data on SoC costs to point out that development costs for a 10nm design are expected to approach $400MM.
GF again made the case that “DIS-integration” can actually offset scaling costs, i.e.:

GF indicates that the yield of high density interposers is high (“..approaching 100%”), even for  full retical sized; 4 metal layer top side, 1 metal layer backside structures.
 GF has come up with the following roadmap for silicon, high density laminate and glass.

Like Amkor, GF has mapped 2.5D requirements by market space and come up with the following.

Also similar to Amkor GF pointed out that the industry needs a low cost high volume source of  high density interposers. Although showing their capabilities for interposer fabrication, interestingly they did not offer themselves up as the solution.  
For all the latest on 3DIC and advanced packaging stay linked to IFTLE………….



Thursday, February 6, 2014

IFTLE 178 IMAPS 2013 continued: Xilinx/SPIL; Nanyang/IME; Cannon, AT&S

Finishing up our look at the fall 2013 IMAPS meeting.

Xilinx / SIliconware

We are all aware of the Xilinx / TSMC / Amkor partnership to develop the first comemrcial 2.5D FPGA module. Since that announcment in late 2010 there have been rumors about Xilinx looking for lower cost second sources. Last summer Siliconware (SPIL) announced the instillation of a dual damascene line for fabrication of high density interposers. [ see IFTLE 158, “2013 ConFab part 2: Amkor and Siliconware”]

At the fall IMAPS meeting Xilinx and SPIL  shared results from their progra to 2.5D 28nm FPGA program.
The high performance FPGA die (it appears manufactured by UMC)  is a 4 slice 28nmchip mounted on a 25 x 31mm 100um thick Si interposer with 45um pitch microbumps. The interposer is assembled onto a 45 x 45mm organic BGA with 180um C4 bumps. The figure below shows thestructure in cross section. SPIL is manufacturing the interpsoer and doing the assembly.

Nanyang Univ / IME
Copper TSV exert thermo-mechanical stress on silicon due to the CTE miss match. This stress can result in variability of the device mobility and mechanical reliability issues. This can be alleviated by using a oxide liner that has a lower elastic modulus such as some of the “low-k” dielectric materials (black diamond) . This would reduce the keep out zone and in addition such materials will lower the parasitic capacitance of the circuit.
These Singapore institutions looked at the use of low-k carbon doped oxides to serve as a more compliant layer TSV insulator layer due to its lower modulus (7.2 GPa vs plasma enhanced TEOS with modulus of 75GPa) . The FEA analysis shown below indicates that the low-K materials “should” lower the stress exerted by the Cu TSV on the silicon. Micro raman spectroscopy on samples verifies that the use of a  low-k liner results in less compressive stress exerted by the Cu TSV on the silicon between the TSV. 
CV measurements show that the capacitance is reduced by 26% ( K of PETEOS = 3.9 vs low-K of 2.88).
[ IFTLE sees no discussion of mechanical reliability comparisons. Since low-k is known for being very fragile, I wonder whether the TSV stress will fracture the low-k material which would show up as less stress on the silicon ?]
Cannon, normally associated with front end (FE) lithography addressed “Lithography Process Optimization for 3D and 2.5D Applications”. Cannon has developed the FPA-5510iV and FPA-5510iZ TSA steppers to support high density processes and to support implementation of 2.5 & 3D technology. A comparison of their specs is shown below.

In a typical backside manufacturing process, patterned wafers are bonded face down to a support wafer before being ground and thinned. The bonding and thinning process causes shape distortion in the wafer. Downstream processes require litho that produces patterns that can overlay such distortions with high accuracy. These systems also employ vacuum assist functions to compensate for large wafer warpage.
In July 2013 AT&S (Austria) and TDK-EPCOS announced that they were cooperating on embedding technology to allow standards development and increased customer acceptance [link].
The embedding technology developed by AT&S is shown below:
The authors propose that the use of PCB real estate is lowest for an embedded component and showed the following comparison to a 3x3m die + 10 resistors packages with a QFN [45mm sq vs flip chipped (21 mm sq) vs embedded 916mm sq].
For all the latest in 3DIC and advanced packaging stay linked to IFTLE…