Sunday, March 23, 2014

IFTLE 184 SEMI Europe 2.5/3DIC Summit : Gartner; GlobalFoundries; TSMC; IMEC

Lets take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.

Gartner – 3D Market Forecast

Stromberg of Gartner gave a market forecast of greater than 1.5M 300mm wafer equiv per month or 2B units / year of 2.5/3D (non MEMS non CIS) by 2018 but then listed several pages worth of technical issues that could affect the forecast.

Editorial Comment:
In emerging technologies like 2.5/3D  guaging market timing and size is an art, not a science but I’m not sure what numbers like this are worth if you preface them by saying they could be impacted by thermal issues, yield issues, design issues and  competitive treats by PoP and  WB devices. Of course all those things are true, but then what kind of confidence do we have in the numbers / timing ?  This is true for all the marketing houses not just Gartner.
GF has been detailing their imminent commercialization of 2.5/3D IC for several years. Their current status report is shown below.
Their response to Interposer TSV formation, front side routing and backside reveal and RDL  issues are shown below. High IO counts require dense interposer frontside routing (i.e. over 1600 wires for a HBM port.

The GF supply chain for 2.5D productization is shown below:


Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.

Another interesting roadmap showed TSMC demonstrating HBM (high bandwidth memory) on CoWoS by 4Q 2014.

IMEC – Cost Analysis

Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50µm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside reveal processing are about equivalent in cost.   

They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill.
This can be compared to the 10 x 100µm TSV costs presented by Ramaswami of Applied Materials shown below:

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………..


Saturday, March 22, 2014

IFTLE 183 RTI ASIP: Tezzaron; Suss / EVG; Packaging of Apple A8

RTI- Architectures for Semiconductor Integration & Packaging (ASIP) is always held in Burlingame CA at years end. It is focused on commercial 3DIC technology and applications and is always a good indicator for the status of the industry.

In the next few blogs we’ll take a look at some key papers from this years conference.

Tezzaron acquires Ziptronix facility outside RTP NC

As we have discussed previously Tezzaron has purchased the former Sematech fabs in Austin and is running the operation as a subsidiary Novati [ see IFTLE 146, “TSMCApple…Novati” and IFTLE 166 “IEEE 3DIC part 1;….Novati” ]

Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing [link].   

In addition Tezzarons Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly. [link] 

Tezzaron, known for its fine featured TSV showed the following process status and an interesting X section of a W TSV connected at M5.


Suss and EVG

Suss and EVG examined their processes and equipment available for thin film handling of 2.5 & 3DIC wafers, namely temp bonding and debonding.      

They are both working with a number of materials suppliers as shown in the Table below. All of them now supply room temp (RT) debonding solutions  

 Temp bonding materials supplier
Brewer Science
Dow Corning
Thin Materials AG
Shin Etsu
HD Micro

 Typical thickness requirements for temporary adhesives are dependent on the interface that is being bonded as shown below.
Both Suss and EVG have recently  introduced eximer laser assisted RT debonding which was first introduced by 3M years ago. [ref]
Amkor, STATS ChipPAC and ASE to package  Apple A8
 DIGITIMES is reporting that Amkor  and STATS ChipPAC will each package  40% of the Apple A8 processor, with the remaining 20% by ASE.[link]
They report that Apple's A8 chip will be a package-on-package (PoP) SoC solution comprising processors and mobile DRAM in a single package.
(TSMC, which is believed to have landed foundry orders for Apple's next-generation A8 chip, has reportedly also secured wafer bumping orders for the processor as part of its turnkey solution.  TSMC reportedly will start ramping up production using 20nm process technology for Apple's A8 chip in the second quarter of 2014.
For all the latest on 3DIC and other advanced packaging stay inked to IFTLE.....



The recent Semi  Industry Strategy Symp (ISS) occurred in Half Moon Bay CA a few weeks ago. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does. Lets take a look at some of the key papers from this conference.


IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

 Volumetric scaling will be critical to future performance enablement
– Tightly coupled modules and components
– 3D stacking and interposer integration

Casey examined the current state of interposer substrates and showed the following comparison:

Linx consultants looked at “Chemicals and Materials in Semiconductor Devices” . IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores. 
Linx lists 3DIC among the major 5 challenges for the IC industry in the future.

Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base .

An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm”. She offered the following roadmaps for 3D applications and TSV dimensions.
and the following CoO Analysis for their  3D process flow:
IHS examined semiconductors in the electronics value chain.  An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:


Our friends at Int Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline)  and 2015 (large decline).
While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.

They also conclude that low power and low cost will dominate the application space for 32nm or less devices.

They continue to predict that cost/gate will no longer be a cost driver.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………


IFTLE 181 IEEE 3DIC contd: Tohoku, ASE, RTI

Finishing up on the IEEE 3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining key papers from the conference.

Tohoku Univ - Lattice Distortions in Thinned Silicon

Professor Koyanagi and coworkers at Tohoku Univ and GINTI [ Global Integration Initiative – see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati” ]
It is accepted that to achieve compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping and local deformation in the stacked die .  Moreover, the weak mechanical strength of the extremely thin die/wafer itself has a potential concern lead to die breaking for 3DIC integration, because thin LSI chip with high density TSVs is highly fragile and more easily damaged. Hence, it is important to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50μm thickness.

Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.

 DRAM chip of 200μm thickness were bonded to a Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured retention characteristics of DRAM cell on these thicknesses of silicon are degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip.

They assume that the band-gap energy in the thin chip is affected by the distortion of the lattice structure, hence effect on a minority carrier lifetime, consequently shortening the retention time of DRAM cell.
Fujitsu – Influence of Wafer Thinning on Backside Damage
 Fujitsu is known for their ultrathin WOW process [ see K. Fujimoto,  Development of Multistack Process on  Wafer-on-Wafer (WOW)”, Proceed.  IEEE Electronic Component Tech Conf, 2010.]  
Ultra-thinning to 10 microns or less of Si wafer is expected to realize small TSV with  low aspect ratio and coupling capacitance. Subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.
The authors acknowledge that further investigations are necessary to find “hidden residual defects” and to understand the influence of thinning on memory devices (see Tohoku discussions above)
ASE / Chiao Tung Univ – Low Temp Bonding
ASE and National Chiao Tung Univ  have studied three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D interconnects.
Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 C. Cu and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa, followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding temperature of 180 C for 50 min
Cu/Ti samples were bonded face to face with a bonding pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min.  They add that Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This last structure is especially significant if one can really do such bonding at 180 C . Their EDX investigation of the interface shows that “…apparently there is a Cu layer at the bonding interface instead of Ti layers…due to lower activation energy at the surface, Cu tends to diffuse towards the surface  …”  IFTLE feels this combination certainly deserves further study.
All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.
RTI – 10um Pitch Bonding of Hetero Materials
Matt Lueck of RTI Int described their successful demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch interconnection of heterogeneous semiconductor die. InP die have been bonded to Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps on 10 μm pitch.
A key technological challenge facing the 3D integration of heterogeneous semiconductors is the formation of high density metal interconnects between dissimilar substrates, such as compound semiconductors (CS) and Si. Due to the difference in the coefficients of thermal expansion (CTE), one can expect: 1) some misalignment between microbumps fabricated on the CS substrate and the Si substrate during bonding at an elevated temperature; and 2) bond interconnects will experience shear strain as the bonded die pair is cooled to room temperature and during any subsequent thermal excursions.

To estimate the magnitude of the misalignment, they calculated the relative change in distance between corner microbumps in a 10 μm pitch 640 × 512 array on CS die vs. Si die. Operability was determined by electrical testing of long daisy-chains of bumps.
The average channel yield was approximately 97% for both InP-Si and Si-Si die pairs translating into the array operability greater than 99.99%. The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8% decrease in channel yield whereas those not underfilled showed a 13.9% decrease.

They conclude that Cu/Sn micro bumps can be successfully and reliably used for integration of InP and Si die.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE…..