Having said that, the 3DIC activity was significant. There were two days of sessions led by Sematech, a workshop held by Alchimer, a workshop by Suss and Semicon TechXSpots sessions such as “Bridging the Gap”. We’’ll cover all of that and more, here at IFTLE,over the next few weeks.
Bill McClean, who correctly predicted the 2010 bull electronics market in March of 2009 [see PFTLE 67 “IC Insights Predicts Fast Industry Rebound at IMAPS Global Business Council”,3/15/2009 ] stated that Samsung is now spending 20% of the worlds electronics capex (~ 10B$). He sees the next downturn coming in 2013 and does not see 450 mm wafers coming till post 2015.
Proteus biomedical CEO Andrew Thompson during his presentartion on how microeletronics was going to affect the medical community shared the remarkable fact that the earths 7B people only 3B of them have a pair of shoes but there are 5B cell phone subscribers! That’s a lot of barefoot people talking on the phone! Another interesting
Gregg Bartlett, Sr VP of Technology and R&D in his plenary presentation on “The Centrality of Silicon” showed 3D IC becoming essential at the 22 nm node as shown below.
Qualcomm has become one of the strongest corporate advocates for 3D IC in the world. For some of their recent activity see [PFTLE 126 “Adv Pkging at the IMAPS Device Pkging Conf”, 04/01/2010; PFTLE 125 “3D IC at Ft McDowell”, 03/27/2010 ].
At the TechXSpots “Bridging the Gap” session Steve Bezuk of Qualcomm shared his views on how 3D fits into mobile device roadmaps. Bezuk’s comment that “The constraints of the low power, mobile market present no fundamental technical barriers to 3D TSV technologies” was music to a 3D advocates ears.
He used the PFTLE “4 Horseman of the apocalypse” concept [ see PTFLE 102, “The 4 Horsemen of 3D IC”, 10/16/2009 to make his point as seen below. He notes that:
- for the heterogeneous stacking designs that they are looking at today, 2D tools appear to suffice
- no thermal issues have been uncovered that do not alreadyexist for todays 2D designs
- todays sophisticated SoC test proceedures looks thik they can do he job for entry level 3D products
Bezuk added that Qualcomm is focused on copper vias middle and that detailed Qualcomm cost models are showing that the cost adder for 3D at 45 and nm should be ~ 10%.
Qualcomms Riko Radojcic, speaking at the Alchimer 3D workshop, echoed the earlier remarks of Steve Bezuk that Qualcomm can “manage the current design flow using current EDA products”. Riko, as a designer, indicated that 3D IC was a matter of managing choices and interactions (which are listed below) .
Riko indicated that thermal and mechanical stress considerations need to be incorporated into design enablement and stack design signoff.
Calvin Cheung at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that ASE sees consumer markets driving the roadmaps towards 3D IC. Cheung indicated that facial recognition and bio-sensing for medical diagnostics were two applications that customers have indicated would be highly desirable if integrated on their PDAs.
During a panel Q&A session Chueng indicated that TSMC will be driving the initial use of interposers and that ASE was on board. “We will need interposers to bond 28 nm low K die…right now it is impossible to stack such mechanically unstable materials into a stable 3D stack” Cheung also sees interposers serving as a platform for IPD (integrated passive devices) which will allow them to get decoupling caps closer to where they are needed and that “Graphics chip sets will also require solutions where the power is not channeled through the memory”, making them another potential application for interposers. At least for the first generation products.
Rich Rice from ASE at the Bridging the Gap TechXSpot, presented the following IC cost breakdown from a recent Prismark report which indicates that Packaging and assembly constitutes 16% of total shipped silicon cost.
Bob Lanzone, at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that Amkor is now focusing heavily on the unit operations required to handle TSV middle wafers from foundries. They have backed off their focus on backside TSV fabrication which Bob feels is well under control. Bob says that F2F (face-to-face) CoC (chip-on-chip) technology has been qualified with Cu/Sn IMC down to 40 um pitch. Below 40 um he feels Amkor will move to some form of direct Cu-Cu bonding.
- 3D IC at the IEEE IITC
- Semicon coverage of Suss, Alchimer, Yole, ITRI, EVG, Sematech, Novellus, Verigy
- 3D at the design automation conference
- A look at the ITRS new roadmap…..and much more
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