……….Continuing our look at the 3D related events at the recent Semicon West exhibition.
The ITRI Ad-STAC program has been discussed previously [ see PFTLE 105 “Taiwanese Focus on 3D IC”, 11/06/2009; PFTLE 99 “3D IC at ITRI”,09/24/2009. At the Suss “3D Bonding and Thin Wafer Handling “ workshop Yu-Hua Chen, Deputy Div Director, announced that there is now a team of 150 fully engaged in 3D design, build and test.
Per their previous announcements they still appear to be on time to have their 300 mm 3D line qualified by the 4Q 2010 as shown below.
Their roadmap now shows CPU + RAM stacking and memory stacking in the 2011 / 2012 timeframe, in sinc with other Pacific rim foundries and assembly houses.