Yole
– FC Market & Tech Trends
Rozalia
Beica, newly appointed CTO of Yole Developpement, examined the FC marketplace.
The FC market is currently growing at CAGR of 19% as a result of expanded use
in memory, consumer electronics and mobile phones. In 2012 bumping capacity of
14MM 300mm equiv. was in place accounting for 81% of all “mid end” capacity.
FC technology
is being reshaped by the demand for Cu pillar bumping (CPB) and microbumps
which are both quickly becoming mainstream. CPB is expected to show 35% CAGR
over the period 2010 – 2018.
FC capacity
is expected to grow in the next 5 years in response to demand from (1) 28nm
CMOS application processor (APE) and baseband (BB) applications;(2) next gen
DDR memory and (3) 2.5/3DIC.
FC Bumping and CPB Forecast 2010 –
2018
There hsas
been reduction of the production cost
for WLCSP packages for the past years. Today, many OSATs are working on further
cost reduction with customized WLCSP package designs that are optimized for
specific market needs.
For example,
omitting the UBM layer on smaller WLCSP devices can reduce costs and may still
meet the market requirement on package quality and reliability. Omitting the
UBM requires 25% less process steps, from 4-mask process to 3-mask process.
ASE reports
on the BLR performance of a 3-mask bump on polymer (BoP) WLCSP design vs a 4-mask BoP WLCSP design for 0.4mm and 0.5mm
ball pitch using tin/silver/copper ( SAC)
and SACNi (Ni doping) solders and reports on failure analysis.
WLCSP (a) 4 mask process with UBM; (b)
3 mask process without UBM;
(c) failure modes for 3 mask process
The polymer
material can be polyimide (PI) or Polybenzobisoxazole (PBO) with thickness of 5um to 7.5um. In most BOP WLCSP packages, ASE
states that PBO is the preferred material for better stress compliance, and
hence better board level reliability.
For 3-mask
WLCSP design, there is no UBM. The solder ball is directly attached to the
redistribution layer, using polymer 2 to define the pad opening. Therefore, the
electrolytic plating copper thickness for RDL needs to be sufficiently thick to
avoid any problems due to Cu consumption during SnxCuy intermetallic (IMC) formation
during thermal ageing. For these reasons the Cu RDL thickness is increased from
4um, on 4-mask WLCSP, to about 8um on the 3 mask process to ensure a reliable
solder joint. the thickness of polymer-2 also needs to increase to 12um
polymer-2 thickness to ensure line coverage. A 12um thick polymer-2 layer
creates processing challenge for PI or PBO, and the thermal stress or residual
stress after high temperature curing needs to be carefully controlled to
guarantee the integrity of package structure.
After board
level reliability test, failure analysis was performed to confirm the failure
mode. The failure modes were classified as failed at PCB side Mode A, failed at
component side Mode B and solder fracture Mode C. In the failure analysis, we
found that BLR failure modes are governed by shear rate applied to the tested
samples. High shear rate test, like drop test, tended to fail at the component
side with IMC fracture (Mode B2) or residual solder on pad (Mode B3). But, for
slow shear rate test, like temperature cycling test, the fail tended to occur
at the solder joint (Mode C). They concluded that 3-mask the WLCSP does not
change the failure mode in either temperature cycling test or drop test.
They
conclude:
- BLR
temperature cycling performance is governed by the WLCSP device size (DNP). The
bigger the DNP, the worse temperature cycling lifetime. This was evident for
both solder materials used in this study, even though the larger device has a
larger solder joint size, and there was a larger difference between SAC405
devices than SACNi devices.
- In general, the 3-mask WLCP has worse BLR
performance than 4-mask WLCSP.
- SACNi solder gives improved BLR Drop test performance
(characteristic life, and first fails) for both 4-mask and 3-mask WLCSP
devices.
- They found the same failure mechanism and failure
modes on 3-mask WLCSP as 4-mask WLCSP.
Ultra-thin chips (less than 50 μm thick) can be
assembled by either on flexible films; i.e. chip-on-foil technology or by
embedding them inside the foil. Initial work by the Institute for
Microelectronics Stuttgart (IMS CHIPS) dealt with attempts to glue attach
Chipfilm dies onto flexible foil substrates. They have now
described research with < 20μm thickness die with a two polymer (BCB and PI)
ultra-thin chip imbedding approach.
Polymers used
for embedding should be flexible and at the same time strong enough to keep the
chip firmly embedded. To achieve an optimal solution for the desired process
IMS used a combination of polymers where BCB serves as the embedding polymer for
ultra-thin chips and the PI as the reinforcement
polymer. The X sectional structure is
shown below.
Two Polymer Embedding of Ultra-thin
Chips
The PI
reinforcement layer provides strong yet bendable reinforcement for the entire
chip stack. The BCB embedding polymer provides excellent electrical properties,
low moisture absorption, compatibility with the interconnect metals and fine
pitch patterning compatibility. The
process flow is shown below. An initial “adhesion lowering layer” is initially
coated on the wafer to allow for package removal once the process is complete.
Ultra Thin Chip Embedding Process Flow
The figure
below compares the warpage of the free standing 4.6 x 4.6mm 20um thick chip to
the chip once bonded to the lower BCB layer of the structure.
NXP-
High Temp Capabilities of Epoxy Molding Compounds
Packaging for
automotive and other high temp applications and for GaN and SiC high temp technologies
requires packaging be able to withstand
high temperatures. Epoxy Molding compounds (EMC) will therefore be subjected to
steadily higher ambient temperatures, possibly reaching their intrinsic
limitations. Currently, few materials
have been qualified to withstand ambient temperatures of greater than 175C.
NXP studied the
degradation mechanism of three types of epoxy molding compounds (A): OCN-based,
Tg greater than 150°C, (B): Biphenyl-based, Tg approx. 120°C and (C): Multiaromatic, Tg approx130°C.
When an EMC
is exposed to air (oxygen) at high temperature, two competing chemical
reactions take place. During oxidation, oxygen gets incorporated into the
polymer chains and the resultant groups (e.g. carbonyl groups) can react with
hydrogen atoms from neighboring chains, leading to an increase in cross-linking
density of the EMC. Oxidation also leads to chain scission, where smaller more
volatile molecules are liberated into the air. Both reactions lead to chemical shrinkage
in the polymer. Thermal ageing in air leads to an increase in intrinsic stress
(due to shrinkage) and a decrease in strength for the oxidized layer. When the intrinsic
stress exceeds the strength of the EMC cracks form on the surface.
It is
expected that some key thermomechanical properties will change after ageing, the
main changes will probably take place only in the oxidized layer.
A number of
(thermo)- mechanical properties were measured like the glass transition
temperature (Tg), Storage Modulus (E’), Loss modulus (E”), CTE below and above
Tg (CTE1 and CTE2) and the flexural strength. All of these properties degrade
with oxidation .
Even before
the onset of external cracks in the compound, it has been shown that ageing
leads to a relatively porous and “open” oxidized layer.
Class
C (Multi-aromatic) have the most stable performance demonstrating that a high Tg does not necessarily imply
higher thermal stability.
CMST
(U Gent/IMEC) – Parylene as a Diffusion Barrier
CMST and
co-workers have studied the use of Parylene [ poly(p-xylyene)] as a barrier
material for biocompatible implants. The packaging of implantable devices needs
to be miniaturized as well as the devices. The barrier layers should be hermetic
, i.e provide a bidirectional diffusion barrier . Parylene C and N are prone to
oxidation at temperatures above 70 C. Testing showed limited water vapor barrier protection,
adhesion issues with certain surfaces and limited copper corrosion (although
only after 170 hrs). Copper diffusion is observed through a Parylene barrier
layer . They conclude that Parylene in
combination with other layers might be a better solution. [IFTLE offers that NO Polymer is a hermetic barrier and as such should
not be used as the main source of hermeticity for implantable devices. ]
For all the
latest on 3DIC and advanced packaging stay linked to IFTLE……………….
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