TSMC / Intel and the Apple A7 processor
Steve Shen of Digitimes [link] reports that TSMC is expected to tape out Apple's A7 processor on a 20nm process in March and then "..move the chip into risk production in May-June, which will pave the way for commercial shipments in the first quarter of 2014… TSMC will utilize 14-fab to manufacture the A7 chips for Apple."
J Lien & J Chang of Digitimes report rumors from "institutional investors" that "Samsung is likely to receive 50% of the A7 processor orders, TSMC 40%, and Intel 10%." [link]
Altera and Xilinx returning to PoP ?? (I hope Not ! )
Digitimes also reports that according to the Chineese language "Economic Daily News," Altera and Xilinx are considering switching to PoP (package on package) technology for their next-generation chips, instead of continuing with TSMCs 2.5D CoWoS process [link]. "Altera and Xilinx are considering switching their packaging orders to Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries (SPIL) as both plan to ramp up their PoP packaging capacity in 2013," EDN said. TSMC, ASE and SPIL all declined to comment on market reports, EDN said.Reportedly yields and cost of trial production using a 20nm production node and the 2.5D CoWoS process at TSMC in past months failed to meet expectations, prompting Altera and Xilinx to seek alternative packaging solutions, said the paper.
[Highly placed contacts at Xilinx and Altera are denying the veracity of this story and I want to believe them.]
DARPA ICECool part II - Applications
Military platforms often cannot physically accommodate the large cooling systems needed for thermal management, meaning that heat can be a limiting factor for performance of electronics and embedded computers. DARPA introduced the interchip/Intra chip enhanced cooling program (ICECool) in June 2012 to explore ‘embedded’ thermal management. [ see IFTLE 119 “ICECool Puts 3D Thermal issues Back in Focus”]
The premise of ICECool is to bring microfluidic cooling inside the substrate, chip or package, including thermal management in the earliest stages of electronics design. The first track of the program, ICECool Fundamentals, has already begun basic research into microfabrication and evaporative cooling techniques.
Under the new ICECool Applications Track, DARPA seeks demonstration of microfluidic cooling in (A) monolithic microwave integrated circuits (MMICs) and (B) embedded HPC modules. For part B Proposers are expected to define and explore intrachip, interchip or hybrid approaches compatible with a 2.5D or 3D configuration, such that they would be compatible with DARPA, DoD, and commercial investments and trends in 3D stacking of silicon chips.
DARPA expects proosed approaches for ICECool Applications to involve embedded thermal management through microfluidic heat extraction in close proximity to the primary on-chip heat source(s), aided by heat flow through high conductivity thermal interconnects and/or thermoelectric devices from sub-millimeter “hot spots” to liquid-cooled miniature passages, as conceptualized in the figure below. An intrachip cooling approach would involve fabricating miniature passages directly into the chip. An interchip approach would utilize the microgap between chips in three-dimensional stacks for the cooling.
DARPA further expects proposers to define and demonstrate intrachip and/or interchip thermal management approaches that are tailored to a specific application that are consistent with the materials sets, fabrication processes, and operating environment of the intended application.
Proposers are encouraged to apply their proposed solution to existing liquid-cooled systems, in which the external thermal management hardware can be redesigned into an ICECool design.
In Phase 1 performers will be allowed 12 months to a) design, fabricate, and demonstrate the
feasibility of the proposed ICECool concept with an appropriately configured Thermal
Demonstration Vehicle (TDV) and to b) establish, through electrical-thermal-mechanical co-simulation, the performance enhancement that can be achieved in the targeted electronic module. Performers will be judged based on thermal performance versus the stated thermal metrics, the simulated performance that would be achieved utilizing their thermal strategy, and their ability to adhere to this schedule.
In Phase 2, selected teams will be allowed 18 months to implement and validate their ICECool strategy in an operational Electrical Demonstration Vehicle (EDV) module and demonstrate their ability to simultaneously meet both thermal and functional performance metrics. In both Phase 1 and Phase 2, it is expected that performers will have significant performance and reliability modeling tasks that flow from the preliminary models that are developed as part of the proposal process.
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