Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.
Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.
Now that we are quickly approaching full commercial production of a number of products, it's probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins' article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.
Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50μm is required to deal with the local hot spots on the thermal test chip they used.
Their study on the impact of TSVs on the temperature profile in the test chips showed that the presence of the die-die connections, such as Cu or CuSn microbumps or direct Cu-Cu bonds, is more important than the presence of the TSVs itself. The Cu TSVs with high thermal conductivity (390 W/mK) are inserted in the Si, which is conductive (150 W/mK at room temperature and120 W/mK at the operating temperature). Conductivity values for the underfill materials are typically 0.2 W/mK for unfilled underfills and 0.3-0.4 W/mK for filled underfills, depending on the amount and type of filler particles. The difference in thermal conductivity between the metallic bonds and the adhesive material is thus two orders of magnitude. As a result, "well placed dummy microbumps, rather than dummy TSVs, can be used to increase the effective thermal conductivity and to reduce the temperature increase in a 3D stack."
Many of you are aware of DARPA's BAA 12-50 ICECool an effort of CALCE's Avi Bar-Cohen within DARPA's Microsystems Technology Office (MTO). ICECool Fundamentals is the initial thrust and first BAA of DARPA's ICECool program.
The specific goal of ICECool Fundamentals is to demonstrate chip-level heat removal in excess of 1 kW/cm2 heat flux and 1 kW/cm3 heat density with thermal control of local sub mm hot spots with heat flux exceeding 5 kW/cm2, while maintaining these components in their usually accepted temperature range by judicious combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects. ICECool Fundamentals is, thus, the first step toward achieving the system performance goals of the ICECool program and will develop the fundamental building blocks of intrachip and interchip evaporative microfluidic cooling.
ICECool Fundamentals will, over an anticipated 24–36 months, develop and demonstrate the microfabrication techniques needed to implement thermal interconnects and evaporative microfluidics in multiply-microchanneled semiconductor chips, and study, model, and correlate intrachip heat diffusion and the thermofluidic characteristics of evaporative flows in microchannel flow loops within individual chips and/or in the microgaps between chips in 3D stacks -- without compromising the combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects in one of several possible semiconductor wafers.
They offer the following schematic as an interchip approach:
and required responses to deliver on the following metrics.
There will be several winners to this first "fundamentals" BAA and hopefully we will be seeing the next generation 3DIC thermal stacking technology evolve from the government-supported program. IFTLE will keep you informed as the winners are announced and their proposed thermal solutions become public.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE......................................