Bob Patti of Tezzaron Semiconductor has been touting the merits of 3DIC for longer than most everyone else in our industry. Bob first announced a partnership with Chartered Semi to scale up his memory through-silicon via (TSV) technology back in 2007 [see PFTLE13: "50$ bonding and Intel announces 'We are ready'"].
Tezzaron has always been at the leading edge, offering 2µm pitch W TSV several years ago. Being ahead of the industry, frankly, they have had issues working through the regular supply chain.
Last week Tezzaron took a major step toward alleviating that problem with the announcement that it is acquiring the wafer fabrication facility of SVTC Technologies in Austin, Texas. You old-timers will recall this as the SEMATECH fab in Austin. Tezzaron will continue the operation of this facility while adding capabilities to assemble its own 3DIC devices. Tezzaron indicates that they will be operating the fab with the same employees in the same location.
The 45th Symposium on Microelectronics (IMAPS 2012) was held a few weeks ago in San Diego. Let's look at some of the 3D and advanced packaging papers presented at this meeting.
When last we discussed Qualcomm it was complaining about constrained supply of 28nm [ see IFTLE 114, "...28nm; nickels and a symbiotic relationship"] but do we have any clarity on exactly what it is trying to build? Maybe now we do.
Gu and co-workers at Qualcomm reported on a memory on logic 3DIC stack consisting of a two-chip-wide IO memory stack bonded to a 28nm logic chip.
TSV are 6µm, wafers are thinned to 50µm, TSV connection is to M1 of the 7-layer copper/low-k interconnect stack. The memory stack has 1200 IO on 40µm pitch. The bottom memory die has TSV, the top die does not need them. Thinned die are shipped either on their carrier (OSAT removes the carrier) or after removal from the carrier on a flex frame.
Negligible shift in electrical parameters are observed after optimizing TSV formation and determining the need for a 5µm keep-out zone (KOZ). No change in bump resistance is seen after 1000 hrs at 150°C and 1000 cycles of temp cycling. Memory function was verified after full assembly of the stack.
Xilinx has been releasing information on its 2.5D FPGA module for the past two years. [See IFTLE 73, "Xilinx shows 2.5D Virtex 7 at IMAPS 2011" and IFTLE 23, "Xilinx 28nm multi-die FPGA, copper pillar advances at Amkor, and Intel looking at foundry options."]
In this latest presentation, Banijamail and co-workers examine the reliability of their 2.5D Virtex-7 H580T which consists of a transceiver chip and two FPGA slices. Interposer TSV are 10-20µm and 50-100µm deep. FPGA chips are bumped on 30-60µm pitch using Cu pillar bump technology.
Different substrate sizes and designs, lid designs, lid materials, and underfills were examined to minimize warpage and maximize microbump and c4 bump reliability. Control of these variables resulted in packages that met JEDEC warpage spec and minimized BGA fatigue.
IFTLE has detailed many times how Applied Materials is making 3DIC a focus area for its equipment business. [see IFTLE 95, "Time flies when you're having fun: Further details on the Micron HMC, equipment suppliers continue consolidation, EVG temp adhesive open platform" and PFTLE 72, "Samsung 3-D 'roadmap' that isn't."]
Eaton and co-workers from Applied Materials now present process detail on how scallop-free TSV can be etched in their Silva etch chamber. Complete scallop removal added ~10-15% to the time to etch a 10 × 100 TSV with 30nm sidewall scallops.
SEMATECH reported on their examination of the copper protrusion issue. While they quote a few past references such as my friends Paul Ho and Jay Im at UT Austin, to give credit where credit is due, they leave out what I think are the key references to the area [see "Researchers strive for copper TSV reliability," Semiconductor International, Dec. 3rd 2009], which include Bob Patti at Tezzaron whose cross-sections first brought the protrusion question to the public eye; Paul SibelrudPaul Sibelrud (then at Semitool) who extensively studied the extent of the problem and the composition of the extrusions; and most importantly Eric Beyne at IMEC who was the first to disclose the thermal anneal solution for the problem.
For those of you new to the area, after TSV are filled with copper and planarized by CMP they are subsequently exposed to >350°C downstream processing during which time Cu, due to a higher CTE, expands more that the surrounding silicon and extrudes out beyond the planarization point and stays there upon cooling due to its plastic deformation properties. This expansion also causes stresses to be generated which in turn require a KOZ (keep-out zone) to be defined so said stresses do not negatively impact the transistor electrical performance.
The goal of this SEMATECH study was to look for "possible mechanisms that cause copper protrusions by varying process conditions." The TSVs studied were 5 × 50 lined with 500nm of TEOS oxide and Ta/TaN diffusion barrier, which were then annealed at 150°C for an hour and CMP'ed. Samples post CMP were annealed at seven different temperatures .
The researchers outline a number of methods of detecting the protrusions and give +/- for them. They chose optical imaging and AFM as their methods of choice and micro raman spectroscopy to determine post-CMP anneal stress.
As expected, stress increases as the post anneal temp increases and copper protrusions range from 50nm to 400nm when annealed (post plating) from 150°C to 400°C. In agreement with the previous studies by Sibelrud, they find that plating bath chemistry has a major impact on protrusion. They link this to whether the copper is in a tensile or compressive state. They suggest that copper grown in a tensile stress state is a significant contribution to protrusions after thermal annealing at high temperature.
Next week we will finish our look at IMAPS 2012.
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