There were several interesting 2.5 / 3D presentations at the recent IEEE ISSCC conference.
2.5D Integrated Voltage Regulator Using Magnetic Core Inductors on Silicon InterposerMinimizing energy consumption is a performance goal of all of today’s devices including microprocessors. Dynamic voltage and frequency scaling (DVFS) is a technique for performing “on-the-fly” energy-use optimization. Implementation of DVFS requires voltage regulators that can provide independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs).
Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, but the primary obstacle facing development of IVRs is integration of power inductors. This work by Columbia University and IBM presents “an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration” by combining magnetic materials, chip-stacking design and a 2.5D chip packaging process. The power converters integrated onto the same chip, or into the same package, as microprocessors "significantly improves computational performance per watt of power consumed
They report that the technology can reduce power consumption, by 10-20% in a typical US data centerInductors are fabricated on the silicon interposer in an elongated spiral with a Ni-Fe magnetic core encasing the copper windings on the long axis. “The Ni-Fe is deposited under a magnetic biasing field so that the hard axis of magnetization forms along the width of the core as shown in the figure. Inverse coupling between adjacent inductors, is utilized to avoid magnetic saturation of the core.” The inductor fabrication involves successive electroplating deposition of the bottom magnetic core, copper windings, and top magnetic core. The windings are electrically isolated from the bottom magnetic core with a layer of silicon nitride, and from the top core with ”hard baked photoresist”.
(Click on any of the images below to enlarge them.)
IBM Stacked Memory on ProcessorThere have been rumors out there that IBM would be applying with their 3D technology in their upcoming Power7 devices. Their presentation at ISSCC may be the first look that we are getting at their early designs for processors stacked with cache memory using TSV technology.
This work describes a prototype 3D system, constructed by stacking a eDRAM memory layer and logic blocks from the IBM Power7TM processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology enhanced to include TSVs. The 3D stack is constructed using 50 µm pitch C4’s joining the front side of the thick processor chip to TSV connections on the back side of a thinned memory. The TSVs are Cu-filled vias that are ~20µm dia and <100 µm deep.Standard design methodologies with some 3D extensions were used to design each stratum. TSV locations for power and clock were pre-defined to match a regular grid. Some sites were de-populated to accommodate the eDRAM blocks.
Tezzaron Technology Used for 2 Processors
Old friend Bob Patti at Tezzaron was involved helping fabricate two of the processor modules shown at this years ISSCC
Georgia Techs 3D-MAPS: 3D massively parallel processor with stacked memory3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5 x 5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density
Tezzaron 3D technology was used to stack two logic dies using face-to-face (F2F) bonding, where the top die is thinned to 12µm and the bottom die is 765µm thick. These F2F pads are used for signal and P/G connections between the two dies. The diameter of a F2F bonding pad is 3.4µm, and their pitch is 5µm. 3D-MAPS uses 235 I/O cells that are placed along the periphery of the core die. Each I/O cell contains 204 redundant TSVs, where each TSV connects between a metal 1 landing pad and a backside metal landing pad deposited on the backside of the silicon substrate. Each backside metal landing pad (56 x 56µm2) is wire bonded to the packaging substrate. The diameter, height, and pitch of a TSV are 1.2µm, 6µm, and 5µm, respectively
University of Michigan Centip3De
David Fick of the University of Michigan showed Centip3De another processor fabbed by Tezzaron. A 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM operating at near threshold voltage. The module has an un-thinned cache layer and a thinned core layer with WB connecting to TSV on the backside.
Hynix Dealing with Process Variation in a 3D Memory StackIn general, commercial DRAM shows large process variation from chip to chip, which causes address access time variation (tAC). In order to reduce the tAC variation, most high speed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption.
Hynix in their paper entitled “A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface explains that this can be an even larger problem for stacked memory die. “For TSV-based stacked dies, large tAC variation results in higher power consumption due to short circuit current from data conflicts among shared IOs”. Since the number of IO might be 512 or more for wide IO DRAM, the additional power consumption can be very high. While it is desirable in mobile DRAM to exclude the DLL because of the power cost , TSV stacked DRAM for high-speed operation partially adopts a DLL in the master die (driver circuitry) . The DLL-based data self-aligner (DBDA) described by Hynix reportedly reduces the data conflict time among stacked dies, consuming 283.2µW during read operation at 800Mb/s/pin. It dissipates 4.98µW in self-refresh mode with the help of leakage-current-reduction controller.
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