Saturday, January 22, 2011

IFTLE 34 3D IC at the 2010 IEDM

With the general belief that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at the IEEEs premier IC conferences namely the ISSCC (Int Solid State Circuits Conference) and the IEDM (Int Electronic Device Meeting).
At the 2009 IEDM TSMC researchers called 3D IC “an enabling foundry technology for 28 nm and beyond” after they studied the impact of 3D thinning ( to ~ 50 μm) and fine pitch bonding on strained and unstrained 40 nm Cu / ELK CMOS and Koyanagi and co-workers from Tohoku University examined the electrical implications of mechanical stress / strain and metal contamination on thinned 3D LSI.[ see PFTLE 117, “ On Copper Diffusion, Gettering and the Denuded Zone “. In 2010 3DIC became even more prominent at the IEDM.

During his 2010 keynote presentation Jim Clifford, Sr VP and Operations GM indicated that scaling could get to expensive and therefore Qualcomm was backing 3D TSV technology and urged the rest of the industry to collaborate on 3D IC and invest in its infant infrastructure.


Dr Kinam Kim, President of Samsung Advanced Institute of Technology (SAIT) in his keynote presentation on the future of silicon technology noted that conventional scaling was becoming more challenging in terms of materials, patterning and electrical performance, and now requires huge capital investments. He commented that current scaling strategy “…is almost unusable for the 10 nm node…”.

Samsung sees mobile processors, FPGA, and high performance ASIC applications will require “ more functionality at greater speeds” which will require “... a heterogeneous device stack with a wide I/O interface and high data rates”. Kim notes that “..the semiconductor industry is adopting 3D IC technology as a promising solution for these devices”. Kim added that short term TSV based IC technologies along with 3D Si interposers will accelerate the adoption of 3D system-in-package (SiP) heterogeneous integration. “..This might be the next driver for genuine 3D IC devices in the future with tremendous benefits in footprint, performance, functionality, data bandwidth, and power”


In their presentation on 3D integration for the 28 node and beyond, TSMC indicates that “optimized fabrication processes and materials selection are critical to achieve high device performance, yield and reliability for 3D technology integration on 300 mm wafers” . They claim to have successfully integrated 3D technology into advanced CMOS foundry processes which is “.. a major step toward 3D production”.

Of interest are the TSMC studies on Cu protrusion and its effects on device fabrication and reliability. They find that the amount and shape of protrusions, (shown in the figure below) depend on several process parameters, including the electroplating processes (ECP), electrolyte selection, impurities co-deposited with Cu, Cu grain size distribution, and post deposition annealing conditions. As the system cools down from thermal excursions, mismatches in CTE between silicon, oxide liner, and Cu fill introduces two un-desirable effects. The first effect is Cu extrusion around the center of the TSV, shown below. The second effect is liner cracking. Having the smallest CTE, the oxide liner undergoes high stresses exerted by the Cu TSV and the Si substrate. The maximum stress concentration is found to be near TSV bottom, where the majority of liner cracks were observed that causes significant current leakage.

It is also shown that residual stress remains in Si substrate after TSV processing. For devices using strain-Si technology, an active device a keep-out zone surrounding each TSV is required to minimize TSV impact on performance.


In a joint program between IBM Yorktown and National Chiao Tung Univ (NCTU) in Taiwan “oxide recessed” vs “lock & key” bonding structures were compared and contrasted.
For the lock-n-key structure, the “lock” part is achieved by recessing Cu, while the “key” part is fabricated with recessing oxide. The recessed amounts of both parts are carefully fabricated to make sure two Cu surfaces can contact during bonding. In addition, the lock-n-key structure allows oxides from both wafers to simultaneously bonded during Cu bonding (Cu-oxide hybrid bonding).

After alignment, wafers were bonded at 400°C for 1 hour under a 10,000 N force in the ambient of 2x10-4 torr. The bonded wafers were then diced and held at 200°C for 70 hr in air to test for corrosion. The lock-n-key structures show clear well-bonded structure, indicating excellent corrosion resistance whereas the Cu bonded, oxide-recessed structures have become significantly corroded. In addition, the bond strengths of lock-n-key structures are higher than those of oxide-recessed ones.


3D induced stresses are one of the key constraints in a 3D design flow that must be controlled in order to preserve the integrity of front end devices. IMEC and some of their consortium members (Panasonic, Qualcomm, Samsung) examined the stress induced by single- and arrayed TSVs, quantifying the stress distribution and determining its impact on both analog and digital FEOL devices and circuits. Stress aware design and the right definition of keep out zone will be needed to optimize silicon area.

From stress modeling studies such and experimental data points, transistor “keep out zones” are derived for both digital and analog circuits. The IMEC researchers conclude that the KOZ for a large matrix of TSVs is over 200 µm for analog circuits and 20 µm for digital circuits and add that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large layout area. Depending on the TSV footprint and the number of TSV required different TSV placements will be optimum (single, row, matrix).

Tohoku Univ

Mechanical stress / strain in thin 3D structures was once again the topic of study for 3D technology veteran Professor Matsui Koyanagi of Tohoku University. The Tohoku group has concluded that high performance 3D-LSI require 104 to 105 micro-bumps/TSVs and a die thickness of ~ 20 μm. They find that mechanical strain/stress and crystal defects are produced in extremely thin of 3D-LSI wafers (~10 μm) not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and underfill curing. Cu/Sn microbumps induce stress/ strain at Si wafer surface, which penetrates deeper for larger bump size and wider for smaller bump pitch. They note that this locally induced stress / strain can result in a 10% change in the ON current of p-MOS transistor.

Koyanagi also reported that the metal of the TSV and microbumps not only induce stress / strain (due to the difference in the CTE between Si and metal in thinned Si substrate but also can be the cause of metallic contamination.

For all the latest on 3D integration and advanced packaging stay linked to IFTLE…

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