In its new incarnation [see PFTLE 100, “3D IC in the City by the Bay” for historical perspective ] the IEEE 3DIC Conference met in Munich under the leadership of European co-chairs Peter Ramm (Fraunhofer EMFT Munich) and Eric Beyne (IMEC). Next years meeting (fall of 2011) will be held in Tokyo with Prof. Mitsumasa Koyanagi (Tohoku Univ) and Mr Morihiro Kada (ASET) as leaders. Below is a photo of this years session chairs and speakers “bookended” by chairman Peter Ramm on the left and old friend Fred Roozeboom on the right.
First we will take a look at cost modeling 3D processes and interposer technology and in hte next blog we will look at some other interesting presentations.
IMEC cost modeling
We would certainly all agree that the many reported manufacturing options for 3D integration could have a different impact on the cost of a 3D-stacked system. IMEC has developed a cost model to compare the costs of different process flows. The model revels a slightly lower processing cost for TSV middle (3D-SIC; 5 x 50 um) vs TSV backside (3D-WLP; 35 x 50 um); backside wafer preparation for Cu-Cu bonding and W2W Cu/Sn bonding as shown below.
Of great interest to IFTLE is the IMEC plot of processing cost (etch, liner, barrier, plate) vs TSV depth. Increasing the TSV depth at a given diameter (i.e increasing the AR while holding the diameter constant) affects etching, liner and barrier and plating negatively. In the chart shown below, one can see that SIC and WLP cross over at about 75 um. The model predicts a 40+% increase in cost to make a 5 x 100 3D-SIC TSV than a similar 5 x 50 TSV. Similar conclusions have been reached by EMC-3D [ see PFTLE 68 “Like Swallows Returning to San Juan Capistrano” ].
The model also concludes that the anticipated lower stacking yield of a W2W stacking strategy results in a higher cost for both the 3D-SIC and the 3D-WLP process flows.
Papers from Fraunhofer IZM – EMFT Munich and RTI Int addressed fabrication aspects of 3D IC Interposers.
Weiland at IZM Munich described a 400 mm sq x 100 um thick interposer with 20 um dia TSV (5:1 AR) on 50 um pitch. The sidewall insulation consisted of thermal oxide followed by O3/TEOS SACVD (sub atmospheric CVD) and the barrier layer was TiW. The 3 layer RDL, built on the TSV is based on photo polymer (not identified) and plated copper. Wafer thinning to 100 um was done with a carrier wafer and temporary adhesive (stable to 150 ˚C to allow backside deposition of low temp CVD SiO2.
Malta of RTI Int examined the fabrication of interposers by TSV first and TSV last processes. In the RTI backside TSV last process TSVs are formed after the front-side thin film processing is completed. It is not necessary to fill the TSVs since dry film resist can be used for patterning of back-side metal after the TSVs are formed. Since the vias do not need to be filled, TSV reliability concerns due to Cu-Si CTE mismatch are also reduced. One of the primary advantages of this approach is that the critical thin film processing is done on a blank Si wafer, with no limitations imposed by Cu-metallized TSVs. However, the TSV processes must be compatible with the thermal limitations of the front-side thin film layers which may include PECVD-TEOS or polymer dielectrics.
The biggest challenge occurs in making the interconnections between the TSVs and the front-side metal during “bottom clear” etch which selectively removes the insulator from the base of the TSV, exposing the metal, while not etching the sidewall isolation. Too much etching can result in high TSV leakage currents, due to sidewall passivation loss, while too little etching can result in high resistance interfaces.
In the TSV first process the TSV are etched as blind vias, from the front surface of the wafer. They are then passivated, coated with seed metal, and plated with Cu and the Cu overburden on the front-side is removed by CMP. The wafers are then thinned using backgrinding and back-side CMP, until the TSVs are exposed. After repassivation of the back-side, the interposers undergo front side thin film processing and backside metallization. A significant advantage is that the passivation “bottom clear” etch is not required, as in the TSV last approach. Also, since there are not other materials on the wafer at the time the TSV are insulated and filled, high temp processes such as thermal oxidation can be used to produce high quality oxide insulation. There is concern over the copper filled TSV CTE mismatch issues. Malta suggests that a way to address these reliability concerns is to “…limit their diameter” but adds that “In order to have small diameter TSVs with an acceptable aspect ratio for processing, it may be ecessary to thin the wafer significantly. Most likely, freestanding wafers can only be thinned to a few hundred microns. Below that, the use of carrier wafers would be required not only for the thinning, but for any subsequent processing which remained” Current studies were done with 100 um dia TSV with 6:1 AR. TSV passivation was 2 um thermal oxide.
Back-side passivation tests was examined with photo BCB and PI. Malta did observe thermo mechanical issues during the curing processes at temperatures of 250ºC and 350ºC respectively. Distortion of the dielectric layers was observed in the areas over the Cu-filled TSVs, along with delamination and cracking of the films. RTI believes this is due to an protrusion of the Cu in the TSVs during the dielectric cure. Anneal tests at 400ºC for 1 hour in N2 indicated that the Cu in the TSV went through a permanent expansion of 1.5-2μm during the 400 C exposure as shown below.
For all the latest in 3D IC and advanced packaging stay linked to IFTLE, Insights From the Leading Edge….