Remembering VLSI Japan
VLSI Japan was an outstanding technical conference which promoted the sharing of information and ideas through the 1990’s and 2000’s. My own memories bring me back to the 2000 VLSI meeting that George Harman, Len Schaper, Jan Vardaman and I attended from the US.
After far too much Sapporo black label at a conference karaoke party, I recall Len and I led the group in singing “Hey Jude” (everyone in the world knows the words to this Beatles oldie).
As we say Sabishii (we will miss you) to VLSI Japan we say youkoso (welcome) to the new CPMT Japan symposium. From my own ancestry I offer the toast “cent’ anni” (may you live 100 years) to the new conference and its participants !
There were several interesting and informative 3D related papers presented at the IEEE CPMT Japan Symp this year that are worth reviewing.
3D stacks are usually joined by metallic bonding using techniques such as solder or Pb free solder bumps, Cu/Sn eutectic or Cu/Cu thermo compression bonding. Non conductive underfill can be used to fill in the space in and around the interconnections to mechanically support the interconnect. It is difficult to flow traditional underfill materials into such narrow gaps and to control material flowing out from the chip edges.
Pre applied non conductive filler (NCF) doesn’t need to flow into the small gaps or flow out over the chip edges. Lamination on structured surfaces demands a fluid nature for the NCF while a rigid material is required for dicing. This combination of properties can be obtained from materials that have temperature dependant viscosity. Such NCFs can flow into the narrow spaces between bumps and be cut with a standard dicing saw.
Pre applied NCF must be transparent, to allow viewing of alignment marks, and must not remain between the bump and the pad during bonding. Toray developed a transparent, low CTE underfill by using nm sized filler particles as shown in the figure below.
To get transparency from a less than 20 µm film requires filler particles less than 50 nm . Toray has achieved optical transparency, a CTE of 37 ppm/C and a 1% wt loss temp of about 350 C.
To insure that the bump / pad area is clean during bonding, the chip with NCF should be heated up to the temp where the NCF changes to a flowable liquid and then pressed into contact with the pad on the other chip in the bonder.
As an alternative solution Toray has also developed a negative tone photo NCF to insure the contact areas are free of underfill material during joining. The material flows at ~ 200 C and has a 1% wt loss temp of 300 C.
When filling TSV with Cu, the overburden is usually removed using CMP. The Cu thickness and topography requires a optimized Cu CMP process for removing the thick Cu layers. Hitachi studied friction force requirements and chemical additives for various slurries in order to develop a high speed removal process specifically for 3D processing. The table below shows both the target values and the ultimate product (HS-C935) performance.
Uniformity of their high speed copper overburden process is shown below.
We have discussed Japan’s ASET consortium several times in the past [ see PFTLE 104, “3D From the Land of the Rising Sun”] For the Dream Chip program Renesas and Rohm are studying thinning and pick-and-place technology for die to wafer constructions. Their specification is to achieve 10 +/- 1 µm wafer thickness stability after thinning and dicing 300 mm wafer devices.
Thinning to 10 µm requires a hard support (carrier) and an adhesive that would both be uniform and is thermally stable enough to resist degredation during grinding and backside processing.
To achieve the 10 +/- 1 µm 300 mm wafer thickness,variation must be controlled in the Si wafer, the adhesive and the carrier as shown below.
Epoxy adhesive with a reported thermal stabilty of 200 – 230 C was examined. After thining to 10 µm no edge chipping or cracking was observed, but swelling of the adhesive and resultant cracking of the thin Si is seen when the adhesive is baked for an hour at 230 C so in reality the material for this application is really only stable to 200 C.
Pick and place of these thinned chips is also a significant technical issue. They evaluated the slide-and-peel method shown below.
When the chip overhang is small the adjoining chip is damaged during the pick operation. When the overhang is to large the lower vacuum attach area becomes too large and he chip cannot be picked up. Conditions were found where the chips could be picked up by the vacuum collet.
Although it will require significant engineering, it appears that there are no insurmountable challenges when it comes to thinning and pick up. It will be very interesting to see the details on the stacking step !
MEPTEC Roadmaps Meeting
MEPTEC will be having a “ Semiconductor Packaging Roadmaps: Applications Driving Requirements” symposium on November 10 at the Biltmore Hotel in Santa Clara,CA. You can find out more about this meeting at their web page.
It will include:
Session 1: Semiconductor Industry Roadmaps: Carving out the Decade Ahead Session Chair: Rich Rice, ASE (US)
Session 2: Panel Discussion -- SATS Technology Development: Merging Internal and Customer Roadmaps Panel Moderator: Joel Camarda, National Semiconductor
Session 3: System-Level Implications on IC Package Design Session Chair:Gary Catlin, Plexus
Session 4: Packaging Roadmaps for Emerging Applications Session Chair: Jeff Demmin, Tessera
For all the latest information on 3D IC and advanced packaging technology stay linked to Insights From the Leading Edge……..