Saturday, June 16, 2012

IFTLE 106 2012 Symp on Polymers for Microelectronics


This was the 15th year that polymer suppliers and users have met in Wilmington DE to discuss the latest advances in polymeric materials. All of the big boys were there including : HD MicroSystems , Dow, JSR, Asahi Kasei, Toray, Nippon Kayaku (MicroChem), AZ and Hitachi Chemical.
Certainly the most interesting bit of information that I learned about a materials supplier was that Alpha started its business in 1704 making cannon balls... cannon balls to solder balls -- now that's a roadmap for miniaturization!

Certainly the main theme, as you shall see below, was the development of low curing temperature polymers that could come close to matching epoxies curing temp (i.e ~175C) while maintaining improved thermal and mechanical properties.   
My plenary presentation was based on the new Yole report "PolymericMaterials for 3DIC & WLP Applications"

Basically over the last 50 years the industry has developed five  basic chemistries for the microelectronics industry. In chronological order they would be epoxies, siloxanes, polyimides, BCBs and PBOs.

(Click on any of the images below to enlarge them.)

If we look at the properties that are important to all or most functions / applications we find 4 broad categories including electrical, mechanical, thermal and misc. (other).

The half dozen key functions that we want these polymers to fill and the seven wafer level applications that we are looking to use them in are depicted below.



Yole projects a 26% CAGR for WL applications over the next few years which will expand the current market to near $1B with significant expansion of applications other than FC bumping.
Since new materials take decades and 10s of millions of dollars to develop, those in the business of wafer level packaging over the next 5-6 years will basically have products from these 5 chemistries to serve the functions for the listed applications.  



The theme for permanent dielectric suppliers at this meeting seemed to be positive tone aqueous developable dielectrics with sub 200C curing temperatures and resultant low stress. The newer packaging scheme such as eWLB require this evolution in dielectric materials because the wafer substrate is epoxy based and  cannot survive the processing temperatures needed to cure polyimides or most PBO and BCB materials. Also, ICs with embedded memory are very sensitive to process temperatures and survivability drops dramatically with increase in temperatures. Lastly, advanced technology nodes such as 32 and 22 nm use lower-k dielectric materials, which are sensitive to the high stresses generated by higher curing temperatures.
Toray is offering a LT series low-temperature curing,  positive-tone photosensitive PI coating with a 170- 200C curing temp and resultant 13 MPa thermal stress. With a tensile strength = 100 MPA, elongation of 30% and Modulus of 2.5 GPa . While the residual stress is reported as 13 MPa, the CTE is troubling at 70 ppm. Asahi Kasei is offering  BM series PIs which reportedly can cure as low as 200C with a Tg of 220C, a CTE of "50-60" and a stress of 19 MPa . HD Micro reported on a new PBO, 8850, with reported better chemical resistance, which can be cured at 250C. JSR reported on their WPR series dielectrics which for positive tone are cresol based with rubber reinforcement. While they can be cured at 200C and have low residual stress ( 20 MPa), their tensile strength (80 MPa) and elongation (7%) are low for permanent dielectrics.  Dow chemical reported on their aqueous developable P6505 BCB which cures as low as 180C (3 hrs) with a resultant stress of 25 MPa. Most of the properties look like the BCB 4000 series with a notable exception that water absorption has risen from 0.2% to 2% for the new version. 
Toray also introduced a siloxane product to replace acrylics for optical applications such as CMOS image sensors, LCD and OLED displays and solar modules. It is 99% transparent at 400 nm and is much more thermally stable than the typical acrylics.
As a general comment, all of these materials are beginning to look like one another which may or may not be a good thing for the industry. As IFTLE has said many times before, you must determine what properties are most important for your application and choose your dielectric accordingly. 
Next week we begin our coverage of the ECTC conference. For all the latest in 3DIC and advanced packaging stay linked to IFTLE......................


Saturday, June 9, 2012

IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple

TSMC Tech Symp

At the 2012 TSMC Tech Symp in April they revealed Reference Flow 12 which shows 2.5/3D firmly entrenched in the TSMC roadmap.
Recent blogs have discussed TSMCs move into the 3D and advanced packaging area. [see IFTLE 94 “Experts discuss InterposerInfrastructure at IMAPS DPCand IFTLE 102 “3.5D interposer technology could somedayreplace PCBs" -- TSMC's Doug Yu” ]
Indeed TSMC isnow showing slides where only the memory and substrates are coming from external sources, making them a turnkey solution for what they are now calling 3.5D [link].


UMC stays in the game
In IFTLE 88 “Apple 2.5D Rumors; Betting the ranch…” we drew an analogy of putting new fab production in place to a poker game in the Wild West – or betting the ranch. Well, the recent announcement by UMC certainly had them tossing their chips into the center of the table matching the recent capacity announcements by TSMC and Global Foundries. The UMC 300mm Fab 12A Phase 5 & 6 in Tainan will extend 28nm production. P5 & P6 will provide advanced 28nm, 20nm, and 14nm capacity, and is scheduled for equipment move-in during the second half of 2013. Total cleanroom area is 53,000m2 and will be capable of 50K wafers per month, bringing total monthly design capacity for Fab 12A to 130K wafers. With the planned P7 & P8, the eight phase fab complex will have a total design capacity of 180K wafers per month.
Cumulative capex for UMC's Fab 12A phases 1-4 is projected at $ 8 billion, with P5 & P6 to add nearly $ 8 billion more. There are further plans for P7 & P8. As we said earlier, only the big time players are sitting at this table. With such investments, UMC is certainly showing that they intend to stay in the game.
 They also announced continued activity in “… BSI CMOS image sensor, 2.5D interposer, and 3D IC TSV to provide a truly comprehensive, leading foundry technology platform”  
Rumors from the ECTC
The IEEE ECTC meeting was last week and for those of you who are unaware, it is the number one show for advanced packaging in the industry. 2.5/3D has grown steadily at this conference and it now appears to be nearing 50 % of the ECTC content [ 50% of 6 parallel sessions for 2.5 days] . There were no major announcements at the meeting, but there were some interesting rumors. My filtering criteria is that I must hear the rumor at least twice from separate sources before I report it on to you.  None of these could be substantiated by the parties involved, but that is not surprising.
 IBM Power8 processor
IFTLE has reported before that rumors were swirling that a future generation of the IBM power chip processor would be using a 2.5D interposer configuration. Very strong, multisourced rumors at ECTC persist that the Power8 is currently undergoing testing in IBM servers and we could be hearing about this major interposer announcement “soon” .
 Intel
If your like me, you have been waiting for 5+ years for the imminent 3D announcement from Intel. Recall that we have been told that the technology is ready but it would be up to the product departments as to when to introduce it. Well, not so good news here. The rumor going around is that we are probably looking at 2017 when 450 is introduced. (Don’t shoot me I’m just reporting the rumor. ) If anyone from Intel would like to deny this and give IFTLE better information please send me an email.
Apple / TSMC / Samsung
Back in IFTLE 88, “Apple 2.5D rumors……” (which I’m told was the most read IFTLE blog of all time) we discussed the fact that TSMC and Samsung are in competition for the next generation , the A6, processor for the Apple iPod, iPad etc.. Although everything is hush, hush, it is clear that TSMC is at least developing prototypes based on their interposer technology. It is unknown whether Samsung is doing the same (but we can hope so).  Two opposing  rumors were making the rounds at ECTC. Rumor 1 had Samsung about to make a 2.5/3D announcement, but rumor 2 had Samsung developing an “unknown technology” that negated the need for TSV and leading them to the conclusion that 2.5/3D would not be needed in the future. The Samsung clamp down on the release on any information on 2.5/3D remains …hermetic . Yes these could in fact be the same rumor, but I, for one, hope not.
Lots more from the ECTC over the next few weeks……………..
For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………………………………….

Monday, June 4, 2012

IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper

Continuing with key presentations from the 2012 IMAPS Device Packaging Conference in Ft McDowell AZ.
Tezzaron Process Technology
Bob Patti showed off two Centip3De, a 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM from the Univ of Michigan and the 3-D MAPS, a massively parallel processor using 64 custom cores stacked with a block 256 kilobytes of scratch pad memory from Ga Tech. For more details on these see IFTLE 93, "2.5/3D at the 2012 ISSCC".

(Click on any of the images below to enlarge them.)

Amkor Discusses 2.5/3DIC


Amkor's Ron Huemoeller reported that 3D vertical stacking is:

- memory and application processor driven
- today focused on 28 nm CMOS and moving to 22 nm
- application processors are near exclusively moving to OSAT finished wafer process flows
Whereas 2.5D Interposers are:
network, CPU and GPU driven
........ mother boards reduced from 10 to 6 layers
........ reduce chip mask layers
........ smaller x, y dimensions
- focused on large package bodies (40 -90 mm , near retical sized Si)
-  both foundry and OSAT wafer flow processes being used
 
He sees both dis-integration of large logic blocks and separation of functions

- allows focus of specific functions which require  leading process nodes
- improves wafer yield
- reduces time to market
- reduces mask layer count at advanced process nodes
Concerning the interposer supply chain:
- laminate (which can theoretically be delivered in large panel format (i.e. 500 x 500 mm ) are being investigated by several "elite substrate manufacturers" [ Unimicron, DNP, Shinko, Kyocera]. Limited to 8 um L/s and 40 um vias on 85 um pads today. 5 um l/s will require stepper and better resists which change the economics. 5 um L/S thought to be many years away. Latency issues will limit adoption as will limitations in va/pad design rules.
- glass can be delivered in large panel or wafer format. Several glass companies [Hoya, Corning, AGC] are investing in capability to support glass interposer technology. Glass faces challenges for CMP / damascene processing.
- silicon in 200 or 300 mm several companies supporting silicon interposers in idle foundry space on legacy node technologies. Amkor finds only 3 foundry players committed to delivering "fine featured" interposers [ TSMC, GF, UMC] with TSMC the only one currently delivering in any quantity.
According to Amkor several foundry sources are interested in manufacturing Si interposers and a couple are already delivering fully functional wafers. Currently design rules  "are aggressive" i.e. less than 2 um L/S and 5 um vias.

Amkor indicated that the predominant interposer designs are what IFTLE has been calling "fine featured" as follows:

When looking at TSV products expected to enter the market in the next few years, Huemoeller offered the following roadmap.

TI Promotes Cu WB
TI has recently announced that all 7 TI internal assembly and test sites are now converted to Cu WB. 6.5B devices have been shipped in Cu WB with conversions continuing. TI which started their Cu WB studies in 2003 are in HVM at the 65 node and have qualified down to the 45 node. 50% of all their interconnect wire is now Cu.
Analog, wireless and embedded products in BGA and leadframe packages are all qualified. Cu shows less wire sweep during package molding and since it has better inherent thermal conductivity it shows better battery life. Next TI will be looking at "high rel" applications such as automotive, military and down hole drilling with Cu wirebonding.



For all the latest in 3DIC and advanced packaging stay linked to IFTLE...................

Sunday, May 27, 2012

IFTLE 103 2012 IMAPS AZ Device Pkging Conf; Fujitsu Low Temp Cu-Cu Bonding

It's been over for a few months now, but IMAPS was a bit slow this year gathering the presentations from their device packaging conference, This is however understandable and excusable due to the untimely death of IMAPS employee Jackie Joyner. So let's begin looking at the 2.5/3D and significant advanced packaging papers.

SSEC Wet Etch for Via Reveal
Laura Mauer of SSEC discussed silicon wafer thinning to reveal Cu TSV. The standard via reveal processis shown below. SSEC contends that a KOH wet etch process can be used for the final Si removal without etching the oxide liner. This can be sealed with oxide/nitride and then CMP'ed to expose the Cu vias.

Wet etch with HF/HNO3 has also been proposed by ASET and shown to have minimal impact on the electrical characteristics of the transistors [link].
Asahi Glass TGV (Through Glass Vias)
Takahashi of AGC discussed the fabrication of TSV in glass. They have been able to fabricate TGV with a  193 nm ArF excimer laser by using short pulse width (20-30 ns). The TGV do have significant slope. Better results are achieved when the glass is processed at elevated temperature ( i.e 200C)


Focused electrical discharge can also be used to process TGV in less than 1 ms. AGC claims that there is no physical limit to TGV diameter using electrical discharge. Electrical discharge TGV show smooth sidewalls and rounded via edges. Similar to the laser process the process requires no masks.

Underfill options - Hitachi, Lord, Dow
Hitachi Chemical discussed non cnductive pastes and films. Packaging in general is moving towards finer pitch and smaller gaps requiring a change in underfill materials and procedures.  NCP and NCF applicable for fine pitch and narrow gaps. In terms of pad finish, Hitachi notes that Cu with OSP "is more difficult to have a good connection."

Lord detailed their screen printable NCP ( Tg = 166 C; Mod = 4.1 Gpa) with built in fluxing agent which allows them to do cu-cu bonding on oxidized cu studs. Similarly Dow presented data on their new pre applied underfill (WUF) films with the following materials properties:


Vacuum lamination is preferred and curing is done at 175C for 1 hr. Voiding seen after bonding can be eliminated by pressure curing or optimizing the film thickness. Initial reliability tests indicate good adhesion through MSL-3- 260 C and TCT cond B.

Fujitsu Low Temp Copper-copper Bonding
Fujitsu described further advances in their low temp Cu-Cu bonding technology [link].
Their unique process uses a diamond bit milling machine to achieve a highly uniform and highly polished (7 nm surface vs 210 as plated) which can be thermo-compression bonded at RT and shows grain growth across the interface at 200 - 250C vs 350 C+ for a  standard CMP'ed surface.




Underfill and Cu bumps can be simultaneously cut together by diamond bit with no residue on bump, but hybrid copper/underfill interface exposed to formic acid before bonding "could not sustain arranged location during bonding process." However, if the interface is bonded first and then exposed to formic acid, "partially exposed," clearly grain growth occurs as low as 140 C.


For all the latest on 2.5/3D IC and advanced packaging stay linked to IFTLE.........................

Saturday, May 19, 2012

IFTLE 102 “3.5D Interposers to someday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predicts Consolidation

3.5D Interposers

At the 15th Symposium on Polymers for Microelectronics held last week in Wilmington DE, TSMC’s Doug Yu, Sr. Dir. of front end and back end technology development,  challenged the current nomenclature for interposers and suggested that the more versatile interposer technology should be called 3.5D instead of 2.5D since it is, and will be, capable of much more than the simple 3D stack.
The term 2.5D is usually credited to ASE's Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3D since the infrastructure and standards were not ready yet.  The silicon interposer, Tong felt, would get us a major part of the way there, and could be ready sooner than 3D technology,  thus the term 2.5D, which immediately caught on with other practitioners.

Yu's new position is that interposer technology actually is more versatile and thus should be called 3.5D since it  not only offer a better thermal solution than 3D, but "...can  some day replace most of the high density PC boards." Yu's position is that this modular silicon technology will need minimum low density PCB substrate to connect the functions that have been fabricated on silicon and will be, in essence, the perfect "fab centric" solution. Yu proceeded to show how future smartphones and tablets could be made up of such simple 3.5D silicon modules. More from the Polymers for Electronics meeting coming soon at IFTLE.

Global Foundries 2.5/3D Announcement

GLOBALFOUNDRIES has announced the installation of TSV production tools for the company's 20nm technology platform. CTO Bartlett announced that they were  "...engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry." The first full flow silicon with TSVs is expected to start running at Fab 8 (Saratoga NY)  in Q3 2012 with mass production expected in 2014. GF is also preparing for  a 2.5D line within its Fab 7 facility in Singapore with a similar time schedule as the 3D line in the United States.

While arch competitor TSMC has announced a one-stop-shop turnkey line which includes all of the assembly and test steps traditionally handled by the OSATS [see: "TSMCrepeats call for foundry-centric 2.5/3D industry"], GF proposes to handle  TSV fabrication (Cu , vias middle) and other front-end steps while typical backend  processes such as temporary bonding/debonding, thinning, assembly and test will be done by their OSAT partners such as Amkor [ see IFTLE 65 "..... GLOBALFOUNDRIES Packaging Alliance..." GlobalFoundries reports that they will define a PDK with its partners, initially they are looking at 6 um vias on a  40-to-50um pitch.

Intel agrees - Its all in the Economics

At the recent Intel analyst day CEO Paul Otellini CEO predicted that the increasing cost of manufacturing in the IC industry would result in consolidation that  will "...only leave two or three companies at the leading edge of chip design." Otellini reports that "Gordon Moore predicted a thinning out of chip fabrication facilities once the cost of a new 200mm wafer manufacturing plant hit $1bn, but he was a little too early."

With the cost of a 300mm fab expected to exceed $5B at the 28 nm node and  450mm wafer fabs that are projected to cost more than $10B apiece few companies will have enough volume to absorb such costs.  

Readers of IFTLE know that we have been predicting this outcome for several years [ see PFTLE "IC Consolidation, Node scaling and 3DIC". Nice to see that Intel  agrees, although this will severely limit options for customes of the latest node technologies. 

If you look at this strictly in terms of economics, HVM players at 22 nm should be limited to :

Logic - Intel, Samsung, ST Micro
Memory - Samsung, Toshiba, Micron/Elpida, Hynix ?

Foundries - TSMC, GF

That's less than 10 total players on the leading edge moving forward. Better start getting used to it !

For all the latest on 3DIC and advanced packaging stay linked to IFTLE...................

Sunday, May 13, 2012

IFTLE 101 Advanced Packaging at IMAPS MINIPAD part 2

Continuing with our examination of advanced packaging at the 2012 IMAPS MINIPAD.

ST Micro reported on stress induced fine pitch copper pillar failures. Compared to solder bump, Cu pillar bumping is known to possess good electrical properties, better electromigration performance and better thermal fatigue resistance . The only drawback is that Cu pillar bump can introduce high stress due to Cu higher stiffness compared to the solder material. Therefore, the stress induced failures become a major issue when Cu pillar bump is built on low k or extreme low k (ELK) chips. In this ST Micro study, fine pitch copper pillar has been assessed vs polyimide effectiveness for fine pitch Cu pillar interconnections having small pillar diameter.

(Click on any of the images below to enlarge them.) 

Vehicle1 (package 2 configuration) used extreme lowk ILD materials. Die were attached on the substrate without underfill and underwent several die attach reflow cycles to induce failure and define the more robust configuration. The no PI leg did not evidence any defect up to 20 reflows but the PI passivated leg showed 100% failure after 20 reflows which appear to be stress induced failures ( likely to be crack in aluminum pads ).


Results after reliability tests show that the implementation of polyimide for fine pitch Cu pillar is not obvious. Thus, in the case of PI configuration, failure analysis reveals three main failure modes: delamination at the Bump/PI/pad and copper stress voiding in the pad metal in stacked vias structures, both occurring during thermal cycles. Delamination in the low-k layers has been also found for the highest die size in the PI configuration. All those analyses have revealed that for the tested configurations, higher stress has been observed with the PI configuration compared to the no PI one.

FEA was done to better understand these results. In the No Polyimide configuration, the stress is spread along the pad structure thanks to the higher copper contact. Indeed, the passivation layers (i.e. SiN and PSG layers) have sufficient mechanical properties to transfer the stress to the beneath layers. In the PI configuration, high peak stress is observed beneath the Copper/Aluminum interface. On the contrary, in the No PI configuration, the stress is spread along the pad structure thanks to the higher contact of Copper pillar bump.

STATSChipPAC looked at some "Advanced Ultrathin eWLB-PoP solutions." eWLB has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and PoP (Package-on-Package) technology.

The table below shows reliability for such stacked test vehicles.


Bernd Appelt of ASE continued the theme of thinner is better with his presentation "Ultra Slim Packages with Ultra Slim Substrates" There is no question as the figure below shows devices continue to get thinner.


 JEDEC package heights are defined as follows:


The ASE package family fits these dimensions as follows:


Substrate thickness vs package thickness are shown on the following chart:

The ASE embedded technology a-EASI (adv embedded assembly solution integration). They are undergoing customer evaluation with embedded actives and passives.


FCI presented the latest n their ChipletT(TM) and ChipsetT(TM) embedded die fan-out packaging based on multilayer flex. We discussed this technology in detail last fall [see IFTLE 83, "Orange County 3DIC Workshop"]
Below we see a nice example of what can be done with this technology, i.e a 50% reduction in footprint by embedding the ASIC die.







For all the latest in 3DIC and advance packaging stay linked to IFTLE......................

Sunday, May 6, 2012

IFTLE 100 IMAPS MINAPAD Addresses Advanced Packaging in Grenoble

"I've been a big fan of Phil's ever since his first blog in August of 2007. Did you know he was born in Hell's Kitchen in New York City? Congratulations to the world's foremost expert on 3D integration on his 100th blog!" -- Peter Singer, Editor-in-Chief, Solid State Technology

Dr. Phil Garrou has been blogging for years on the evolution of semiconductor assembly and packaging technologies. In his first 100 blog posts, he's covered the emergence and explosion of 3D packaging, and most recently, the "2.5D" innovation of interposers.

To celebrate Dr. Garrou's 100th post to Insights from the Leading Edge, we've compiled a list of his top 10 best-read recent blogs. You'll find them at the end of this post..................

IMAPS France held the 2nd Micro/Nano-Electronics Packaging, Assembly, Design and Manufacturing Forum (MiNaPAD) in Grenoble in late April.

Jean-Marc Yannou, President of IMAPS France gave a Yole market update on 3DIC and TSV interconnects indicating that Wafer-level-packages are the fastest growing semiconductor packaging technology with more than 27% CAGR in units and 20% in wafers over the next 5 years to come.

(Click on any of the images below to enlarge them)

Yannou also repeated rumors that "Power 8 by IBM believed to be based on 3D interposers; Haswel, Intel GPU on 2.5D interposers for laptops with lots of on board memory and ultra large data bus. "
Leti gave an update on the 3DICE program being done under the European Unions 7th Framework with partners Datacon, Disco, EVG and ST Micro. Below find the unit operations that are part of the program and those responsible. They have concluded that B2F has less operations and is easier to accomplish than F2F.

Back to face attach can be done with die attach film, full sheet bonding layer or patterned bonding layer.

B2F pick and place with a Datacon 2200 can reportedly handle 20um thick die with 7um accuracy in 3 sec. Plasma stress relief allows for thin die handling by increasing die strength.

Thin die encapsulation can be accomplished in several ways i.e by conformal CVD deposition (oxide or parylene), by spin/spray coating of solutions (BCB, PI, ALX) or by film lamination. Die are bevel cut at 45 degrees to make subsequent metallization easier.

Thermo-mechanical stress in these combinations were examined.






EVG gave more details on the release process for their ZoneBond TB/DB (temp bond/debond) process.


- Adhesive ring dissolution is enhanced by magasonics                                                                                   
- Low force, room temperature separation                                                                                                        
- Compatible with both glass and Si carriers                                                                                                       
- Adhesives are (solvent)cleanable                                                                                                                    
- Platform enables use of a wide range of materials, i.e. ZoneBond Open Platform

The anti sticking layer showed a temperature stability up to 300C for 20 min. Carrier wafers were bonded and debonded 25x.

Rolf Aschenbrenner of the Fraunhoffer IZM made an in depth presentation on "Molding
technologies  - A new way for system integration" specifically looking at options for today's transfer molding and compression molding technologies.


While transfer molding has been used for years to make plastic packaged parts, compression molding has recently become in vogue as part of the embedded chip technology package, i.e molded reconfigured wafers.


They propose the following roadmap for system integration with molding.


ST Micro presented some electromigration details on SnAgCu interconnect for WLB packages.
They find that:
- IMC induces resistance increase right after stress beginning
- Electrical open is due to voiding in solder, at Cu3Sn interface, after Cu6Sn5 disappeared
Since the electrical opens are due to voids at the RDL/solder interface a solution is to insure that the enclosure around the solder ball is large enough and increase the RDL thickness as much as possible.  


We will have more MINAPAD review in next week's IFTLE.

For all the latest in 3DIC and Advanced Packaging stay linked to IFTLE..........................

10 Must-Read Insights from the Leading Edge:
1. Apple and TSVs, top chip makers, and "betting the ranch"


This post investigated Apple's possible move to TSVs for its A6 chip, and compared capex numbers to the Western trope of "betting the ranch." Apple's semiconductor roadmap, and the advanced packaging technology of TSVs combined for a compelling read. Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/02/iftle-88-apple-tsv-interposer-rumors-betting-the-ranch-tsv-for-sony-ps-4-top-chip-fabricators-i.html

2. LED market is about to explode

While Insights from the Leading Edge covers a great deal of 3D packaging news, that doesn't mean that there are no other very significant packaging evolutions and market opportunities going on at the same time. Certainly the LED space is one of those, Dr. Garrou said, and readers agreed.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/11/iftle-75-led-market-is-about-to-explode.html

3. Bidding Adieu to Lester Lightbulb

Lester Lightbulb has become something of a favorite character on Insights from the Leading Edge, as Dr. Garrou carries out an in-home energy/cost savings analysis of conventional incandescent lightbulbs, CFLs, and LEDs.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/08/iftle-63-bidding-adieu-to-lester-lightbulb.html

4. Advances in CMOS Image Sensing

In the fall of 2007, Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). The next step of circuit repartitioning and stacking was interrupted by back side imaging, which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel. Now, we consider today's CIS advances.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/02/iftle-89-advances-in-cmos-image-sensing.html

5. Cell Phones and Memory Consolidation

The cellphone continues to pull in the functionality of digital cameras, PDAs, GPS navigators, mobile TV and numerous other applications. It is quickly becoming the dominant market driver for virtually all of these functions.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/10/iftle-69-cell-phones-and-memory-consolidation.html


6. How Xilinx fit 6.8B transistors on its 2.5D FPGA

Garrou reviews Xilinx's new FPGA, with 10,000 connections on a silicon interposer, using "2.5D packaging."

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/10/iftle-73-xilinx-shows-2-5d-virtex-7-at-imaps-2011.html

7. MEPTEC 2.5, 3D and beyond

Reporting from MEPTEC and SEMI's "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference in 2011, Dr. Garrou shares highlights from Amkor, GLOBALFOUNDRIES, and other presenters.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/11/iftle-77-meptec-2-5-3d-and-beyond.html

8. Fine Pitch Microjoints, Cu Pillar Bump-on-Lead, Xilinx Interposer Reliability

Dr. Garrou looks at packaging activities at the 2011 ECTC, including presentations from Qualcomm and STATS ChipPAC, Fraunhofer IZM, Xilinx (interposers!), and others.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/07/iftle-58-fine-pitch-microjoints-cu-pillar-bump-on-lead-xilinx-interposer-reliability.html

9. TSV from 1999 to today, and more on the Micron HMC

Dr. Garrou shows us the evolution of TSV from 1999 through to today, checks in on MU's HMC, and analyzes some recent packaging news.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/04/iftle-95-3dic-time-flies-when-you-re-having-fun-further-details-on-the-micron-hmc-equipment-su.html

10. Defining 3D, and Canon's packaging equipment foray

Garrou explains the variety of 3D packaging terms with a little help from "Raymond J. Johnson Jr." He also notes Canon's back-end equipment entry.

Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/08/iftle-62-3d-and-interposers-nomenclature-confusion-equipment-market-shift-to-pkging-continues.html

Here's to 100 more Insights from the Leading Edge blog posts!