IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.
Volumetric scaling will be critical to future performance enablement– Tightly coupled modules and components
– 3D stacking and interposer integration
Casey examined the current state of interposer substrates and showed the following comparison:
Linx consultants looked at “Chemicals and Materials in Semiconductor Devices” . IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores.
Linx lists 3DIC among the major 5 challenges for the IC industry in the future.
Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base .
An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm”. She offered the following roadmaps for 3D applications and TSV dimensions.
and the following CoO Analysis for their 3D process flow:
IHS examined semiconductors in the electronics value chain. An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:
Our friends at Int Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline) and 2015 (large decline).
While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.
They also conclude that low power and low cost will dominate the application space for 32nm or less devices.
They continue to predict that cost/gate will no longer be a cost driver.
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