IFTLE put together two sessions on packaging which were jointly sponsored by IEEE CPMT and ConFab.
The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high density interposers to the industry. [see “Siliconware announces entrance into high density 2.5D interposer market”].
IBM Orthogonal Scaling
Subu Iyer , IBM Fellow, lectured on his theme of “orthogonal scaling” . His premise is that classical silicon scaling is saturating and we need orthogonal approaches to “scale all aspects of the system including footprint and power”. Subu sees scaling continuing down to the 7nm node, but “the cost per transistor has begun to saturate”
He predicts that the next component of Advanced System Integration will be 3D Integration:
- large interposer platform for heterogeneous integration
- Die Stacking
- stacking of logic die (high and moderate power)
- stacking of memory die (low power)
- Wafer level stacking
His example of stacked memory is the Micron IBM program on stacked memory:
TI Thins Down Packaging
Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G
Iyer points out that while Package families are proliferating, each package type has a “sweet spot” combination of cost, performance, form factor and reliability, driven by:
•Electrical speed, power distribution and noise immunity
•Thickness, weight, PCB area consumption
•Board level reliability (BLR, drop)
•Technical maturity vs. risk in high-volume manufacturing
•Compatibility with Si process
Anderson of STATSChipPAC points to smartphones and tablets driving our industry right now.
For all the latest on 3DIC and Advanced Packaging stay linked to IFTLE.........