There were 180 papers and over 20 posters. Major topics were: Advanced Packaging, Substrate & Interposer, 2.5D and 3DIC Packaging, Design/Modeling/Reliability, Thermal Management, Materials and Process, Printed Electronics, N-MEMS, Optoelectronics, Power Devices, and Biomimetics. In addition, the Japan ASET consortium, Taiwan and Korea held special sessions. IFTLE will cover key presentations over the next few weeks.
Lets first take a look at the ASET special session. The ASET “Dream Chip” program has recently ended in Japan.
The were able to bond 10um pitch bumps (see figure) using a flip chip bonder equipped with infrared alignment optics they found that they could observe alignment marks and adjust the chip position during the bonding process, even when the solder was molten. Most importantly they could eliminate the miss-alignment caused by joining non flat chips an due to thermal expansion of the tool head.
(3) correct alignment for offsets caused by impact of the chip touching the substrate
(4) final align during the bonding while the solder is molten.
Dicing and stacking are important technologies n 3DIC assembly. Bumps on the wafer backside make it difficult for general dicing tape to achieve both high quality dicing and pickup. For tight pitch, small bump bonding it is also difficult to inject underfill into the narrow gap between the dies.