Eric Beyne of IMEC took a look at 3D challenges and progress. The standard IMEC TSV are 5 x 50um for 3D stacking moving in the future to 3 x 50 and for 10 x 100 for 2.5D interposers.
Beyne notes that nearly all options for debonding from carrier wafers are moving to RT solutions. The previously well accepted slide debonding has a small process window and is difficult with bumps on the glued interface. Brewer Science in conjunction with EVG and Suss Microtech are now promoting the Zonebond process which uses a RT release process.
As a cost reduction option, IMEC is studying the elimination of the CMP process for wafer thinning to 2um TTV on 300mm wafer down to 50um thickness. Beyne favors laminated WUF (wafer level underfilling) vs NUF (no flow underfill pre applied to the substrate) commenting that "Probably lamination is the way to go since it covers the fragile ubumps with UF before the assembly process so it's better to handle." In addition one achieves lower surface topography using WUF.
Ted Tessier, CTO of Flip Chip Int (FCI) addressed their embedded die packaging JV with Fujikura. Fujikura’s “WABE” technology (Wafer And Board Level Device Embedded technology) involves stacking and lamination of multiple layers of Cu/PI printed circuit layers around embedded, thinned die and passive components and via filling with conductive paste. Packages can be fabricated in either a face up or face down orientation with backside thermal via options available for improved thermal performance. Multiple die and passive components can be integrated at die spacing as tight as 100um. Passive components can be embedded as well. Processing panel size is currently 250 x 350mm.
Prof Muhannad Bakir of GaTech addressed his specialty 3D stacking with liquid cooling where significant reductions in power and temperature can be achieved. Most agree that some sort of liquid cooling will be necessary for server farms in the future to reduce power usage.
Stephen Pateras of Mentor Graphics looked at the challenges and solutions for 3DIC test.
Gusung Kim CE of EPWorks, the Korean startup offering interposers indicated that customers want interposers at the same prince as high end laminate, i.e. $300/wafer for a 300 mm wafer of interposers. Kim offers glass interposers but sees most programs currently moving forward on silicon. He sees 100 um TGV (through glass vias) doable (in 100 thick glass) , but customers are asking for 10 um TGV.
David Butler, VP of Marketing for SPTS gave a nice update on their equipment for Via Reveal - High Rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing.
SPTS recommends stopping the grind ~5-10um above the TSV so you don’t expose Cu because exposed Cu would migrate. Then one selectively etches Si to ~5-7um below the oxide cap without removing the oxide. The surface is then coated with nitride (for migration barrier) and then oxide, then, after resist definition, Cu is exposed by oxide etching and RDL is built upon the exposed Cu studs.
In the SPTS tool different etch modes are used to control the etch uniformity which reportedly is typically +/-4% with a built-in etch stop process.
Low Temperature (175C deposition ) SiN Barrier is in 300mm production on CMOS image sensor. It is reportedly a dense film with <100MPa residual stress and excellent adhesion and electrical properties. Low Temperature PE-TEOS SiO2 is deposited at 175C with low leakage and high breakdown voltage. Etch and deposition are available on one or multiple platforms.
Coming up next -- an extensive review of the RTI 3D ASIP Conference.........
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