Semi and SEMATECH Lets Get it Straight
A SEMI representative got in touch to let me know that, while SEMI and some people from SEMATECH work together on 3D-IC standards, the two organizations do not have an alliance on TSV. “Both SEMI and SEMATECH are taking key leadership roles in the discussion and promotion of standards for 3D-IC technology. SEMATECH is working with SEMI on assembling standards committees and task forces. Working with SEMI, SEMATECH's goal is to leverage standards to head-off potential show-stoppers.”
“SEMI International Standards is very involved in 3D-IC manufacturing standards. The SEMI 3DS-IC Committee was created in late 2010, and has several activities underway in three task forces. The Inspection and Metrology Task Force is measuring the properties of TSVs, the Bonded Wafer Task Force is working on parameters for bonded wafer stacks, and the Thin Wafer Handling Task Force is developing standards for transport and storage. In addition, a new task force to address trimming of device wafers and carrier wafer dimensions is expected to start work at the 3DS-IC Committee’s next meeting on Tuesday, July 12, 2011 at SEMICON West 2011. The committee is currently chaired by Applied Materials, Qualcomm, Semilab, and SEMATECH. [link][link] and [link]
They also correctly noted that “3D Interconnect Wiki: Stress Management for TSVs” (http://wiki.sematech.org/ ) and the Wiki site (http://www.semiwiki.com/forum/f2/ ) are SEMATECH not SEMI sites.
Glad you all are paying attention, thanks for the corrections and I hope that straightens it all out.
Mentor Graphics 3D-IC Test Solution
Mentor Graphics Corporation recently announced their complete Mentor test solution for 3D-IC, Tessent® v9.4 which will be released May 2011 [link].
The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.
The Tessent test solution reportedly addresses the three main challenges of 3D-IC testing:
- the need for higher KGD test quality to ensure acceptable package yield
- the ability to enable comprehensive testing of all die within a packaged stack
- the ability to test all die interconnects after packaging
KGD is addressed by:
- Support for advanced fault models, including at speed testing in addition to normal “stuck-at” and bridge testing.
- Test pattern compression, which enables higher test coverage while lowering the cost of test by reducing tester memory requirements and test time.
- Hierarchical test capability, which simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips, limited by I/O pin count, routing congestion, or, in the case of 3D-ICs, inter die test paths
- Integration of automatic test pattern generation (ATPG) and built in self test (BIST) techniques to achieve highest coverage at the lowest cost.
3D-IC Test Challenges After Packaging
In 3D-IC stacks, each of the die must be re-tested after the die have been packaged to make sure they remain fully functional. Post-package test is the first opportunity to test all the TSV or interposer connections between die for proper connectivity and at-speed performance. For processor and memory stacks, the memory bus interface logic must also be tested at full speed.
Test point access is a problem because the bottom die is the only one with direct access pins. IMEC has proposed extensions to IEEE 1149.1 (which defines standard test access points0 to allow application of tests in multi-die stacks Their TSV-based 3D test architecture requires supporting methods for routing test data through the stack, and methods to re-sequence test patterns as appropriate for the extended scan chain paths. The Tessent tool suite provides support for implementing the IMEC extensions.
Tessent ATPG and BIST test products reportedly work together to minimize test development effort and to enable parallel testing to increase test throughput.
RAMBUS
When looking at the options for mobile memory moving forward Holt proposes that the industry could continue to evolve todays technology based on low-power DDR2; switch to the newly announced wide I/O memory interface or use the Rambus designed XDR mobile memory solution.
SanDisk
Yoram Cedar, CTO of SanDisk took a look at flash memory.
Cedar expects to see a 5X increase in flash usage in the next 3 years :
Cedar concludes that NAND scaling will need new technologies in ~ 2014 and that “3D Read/Write Memory Will Likely Be the Successor to Floating Gate NAND Flash Over The Long Term” Note 3D here does not refer to TSV technology but rather as shown below.
Penn State
Yuan Xie, long time 3D practitioner from Penn State showed that 3D should have significant cost advantages over scaling at the 32 and 22 nodes.
What are the novel architectural designs enabled by 3D integration ?
- Latency (fast interlayer interconnect)
- Bandwidth (high number of connections bw layers)
- Heterogeneous integration
- Cost benefit
What “Killer” applications could benefit from the unique features 3D can bring ?
- High-capacity memory
- Multi/many-core ?
- Exascale computing ?
Kyowin Jin – Hynix Semiconductor
Jin showed a Hynix 3D roadmap that shows prototype development for 3DS-RDIMM and for 3DS-DDR3 in 2-11 and ultra wide IO development in 2013 as shown below:
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