Samsung, who first revealed 3D TSV stacked memory prototypes in 2006, announced 40nm 8GB RDIMM based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology in Dec of 2010. Samsung claimed the 3D TSV technology saves up to 40 percent of the power consumed by a conventional RDIMM and improves the memory chip density. This DRAM chip was suggested for servers to reduce power consumption and save space. They said Samsung planed to apply the higher performance and lower power features of its TSV technology to 30nm-class and finer process nodes.
Previous generations of mobile DRAMs used a maximum of 32 pins for I/O. The new wide I/O solution which has 512 I/O (up to 1200 total) pins can transmit data at a rate of 12.8-Gbytes per second resulting in a significant improvement in processing power. In addition it reportedly reduces the power consumption by 75% by reducing load capacitance. It is expected to replace low power DDR2 DRAM (LPDDR2) which runs at approximately 3.2-Gigabytes per second according to Samsung.
Following this wide I/O DRAM launch, Samsung is aiming to provide 20nm, 4Gb wide I/O mobile DRAM sometime in 2013. Traditionally "wide" parallel interfaces have been more expensive to manufacture and package. Samsung claims, however, that its 1Gb memory chip with wide bandwidth can be installed instead of a larger amount of smaller chips which results in reduced costs and higher performance.
The die area is 64.34mm2, about a 25% increase when compared with 1Gb LPDDR2. This comes mostly from the increase in number of circuits to support 4-channel and 512-DQ feature. The whole chip is made up of 4 partitions which are symmetric with respect to the chip center, and each partition consists of 4×64Mb arrays, peripheral circuits and microbumps. To reduce power consumption in 512b I/O operations and to support high data bandwidth, I/O driver loading is reduced by adoption of 44×6 microbump pads per channel, which are located in the middle of the chip. The microbumps are 20×17μm2 on 50μm pitch. A fabricated TSV has 7.5μm diameter, 0.22 to 0.24Ω resistance and 47.4fF capacitance.
The SEMI ISS meeting (Industry Strategy Symposium )[link] is an annual January event in Half Moon Bay, CA where industry experts and other economic prognosticators make predictions about the upcoming year for the semiconductor industry. [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage]
When looking at capex by region (2011 projected vs 2005) we see NA holding constant, Japan and Europe going down while Taiwan and Korea are going up.
When looking at growth by geographic region IBS sees China becoming 50% of total consumption by 2012-2013. This means foreign supply will remain a significant portion (ca. 90%) of consumption out into he future (2015)
Reitterating his prediction of last year [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage] Jones still sees only Samsung , Intel and maybe ST Micro as IDMs with their own 22 nm logic lines. The reason for this is again explained in terms of the “cost of developing the next generation process technology” as shown below.
For the first time since we have started following the scaling roadmap, Jones sees an increase in cost / gate at the 22 node.
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Hope to see many of you at the IMAPS Device Packaging Symposium in AZ next week !