Meeting General Chair was Dave Seeger who at the time he signed up was on loan to SRC here in the Research Triangle, but since has moved back to IBM in NY. Technical Chair was Sara Paisner from Lord which is headquartered here in the RTP area.
This years meeting had a significant 3D focus with several professional development courses and 5 sessions which included a panel session on “Roadmaps, Technical and Business Progress” We’ll first take a look at 3D and in the next blog look at other topics in in advanced packaging.
3D IC Panel session
The 3D panel session was headed up by RPI Professor James Lu, panelists are shown below:
IMAPS 3D Panel: Phil Garrou (Microelecttronic Consultants of NC); Nick Sillon ( Group Manager, CEA Leti); Klaus Hummler ( Sr Principal Engineer, Sematech); Urmi Ray ( Sr staff engineer, Qualcomm); James Lu (Professor RPI); Rozalia Beica (Program Director, EMC3D); Dorota Temple ( Program Director, RTI)
When asked about the 3D commercial timeline I commented that roadmaps of many companies (TSMC, UMC, Elpida, ASE etc.) now appeared in sinc and all point towards commercialization in the 2011-2012 timeframe. Ray commented that Qualcomm, a very public supporter of 3D IC technology , sees “two years out (2012)” as “about right”. Hummler was a little more hesitant about timing indicating that “…Nokia is pointing towards product introduction in 2013 but we believe this will be a stretch”. Beica indicated that 15 3D lines were going in place across the world (I assume this included commercial, university and institute lines)
When asked about standards, Ray, herself involved in several standards initiatives, pleaded for more work on standards “now”. Hummler commented that for fables companies standards are a “matter of survival” .
When questioned on the role of consortia and institutes, Sillon responded that “…the role of consortia is to show demonstrators of what can be done with 3D” .
Temple reminded the audience that 3D allows “.. separating digital from analog layers which results in lower power product developments” She also pointed out that we may need what she called “Second generation OSATS” which would be skilled in “..processing not usually done by the OSATS today”.
As we have noted in the past Sematech’s role in the 3D IC infrastructure is to">drive convergence of the materials/equipment solutions by:
– creating roadmaps and standards
– working with others including Member Companies to drive convergence
– industry consensus building through workshops and forums
Klaus Hummler, who has recently moved to the Sematech Interconnect program from siXis, discussed their technical focus area namely “Via-middle” ( TSV’s formed after FEOL and before BEOL) with the following attributes:
• TSV before 3D stacking
• Wafer thinning before 3D stacking
• Back-to-face bonding
• Die to wafer bonding
• TSV diameter 5 μm
• TSV pitch 10-50um
• 20-50 μm TSV depth
Long time readers will note that this is exactly where IFTLE (and PFTLE) has been pointing you for the past 3 years.
EMC-3D / Applied
The name Rozalia Beica has become synonymous with 3D IC in the past few years. Rozalia has been one of the “faces” of the EMC3D consortium [ see PFTLE 47, “3D IC Questions and Answers from the EMC-3D Consortium” After the acquisition of Semitool by Applied Rozalia rejoined the Semitool business unit of Applied Materials working in their 3D program. Processes supported by EMC3D are shown below:
Applied has put together a lineup of tools to address TSV fabrication as shown below (sorry for the small print). Beica reports that Applied, at their Mayden Development center 3D line have run more than 50 integrated demos.
Beica reported that their newer via fill processes show a 50% reduction in overburden and significantly purer copper which results in significantly less Cu extrusion (Cu pumping) and micro voiding.
Paul Enquist, CTO of Ziptronix reports that their direct bond oxide technology catching on with fabricators of backside illuminated CMOS image sensors. Enquist also shared the first released cross sections of a 10 µm pitch, 463,000 connection daisy chain built with the Ziptronix DBI process with Cu filled TSV fully protected by barrier layers (below). Enquist reported a 99.999% yield on such structures.
John Lannon, Sr engineer at RTI Int described the RTI bonding process developments. He warned the audience of electrical failures during reliability testing of 3D test vehicles bonded with Cu/Sn/Cu intermetallics, “…the yield goes to zero after 96 hours standard autoclave testing” Lannon added “ …standard epoxy underfills do not seem to solve the problem, but we have found a silicon underfill that allows device survival through the autoclave testing. More work is needed to completely understand this issue and all potential solutions“ An interesting dialog occurred during the question and answer period of Lannons presentation. An unknown questioner from the back of the room stated that Cu/Sn/Cu bonding used by so many of today’s 3D IC practitioners was nothing more than copper pillar bonding and that (paraphrasing) “…copper pillar bonding is patented by APS and anyone practicing this technology must be licensed by APS”. APS is of course Avanpack in Singapore and indeed I am aware that Amkor, Unisem and Flip Chip Inc have taken out such licenses. I do not support or reject the questioners statement without further study (yes – I do serve as an expert witness !) but I certainly do bring it to your attention.
Rhett Davis, Professor of EE at NC State showed much od the work that he and fellow Professor Paul Franzon have been doing in the 3D area. 3D specific designs were shown that achieved 65% power reduction and an 800% increase in memory bandwidth.
Jeremy McCutcheon of Brewer Science reviewed their Zonebond process (link) showing the audience significant details on the carrier removal step once the wafer is laminated to a film frame. McCutcheon warns that “… solvent strip on film frame an issue since some solvents attack the glue on the film frame. This step must be done properly”
Between now and the end of the year IFTLE will be looking at:
- Napa KGD conference
- IEEE ESTC Conf
- IEEE 3D Test workshop
- RTI 3D ASIP Conf
...as well as any and all announcements and rumors that you need to be aware of.
The RTI ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) will be held in Burlingame CA on Dec 8-10. 3-D ASIP is focused on technology advancements, business issues and infrastructure development. Among the many invited speakers are Erik Volkernik CTO of Verigy, Subramanian Iyer of IBM, Doug Yu of TSMC, Ho-Ming Tong of ASE, Bob Patti of Tezzaron, Arif Rahman of Xilinx, Marc Scannell of Leti, Bob Lanzone of Amkor and many, many other industry experts. Hope to see you there.
For all the latest in 3D IC and advanced packaging stay linked to IFTLE………………………….