IFTLE 16 the 2009 ITRS Interconnect Roadmap - a Chance to Say “I Told You So”

The 2009 edition of the ITRS Roadmap didn’t become available till this summer. This is the first roadmap where 3D IC has become an important and integral part of both the Interconnect and the Assembly and Packaging sections. It is certainly worth our time to look at what they have to say about 3D and other related topics. The full reports can be accessed here (Interconnect; Assembly and Packaging).


The ITRS Interconnect Roadmap


Credit goes to the Interconnect committee for two reasons:
1) Unlike JEDEC [see PFTLE 128 “3D IC Standardization Begins” ]the committee list their members so you can tell exactly who was involved with generating the document. Bravo gentleman !

2) I have, in the past,been a harsh critic of the mistakes this committee made in the late 1990’s when some absurd predictions were made about where low K was going and by when [see PFTLE 44 “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmap”,9/11/2008]. As you can see in the fig below, the projection the Low-K probably will not get below 2.5 with current material sets is a much more rational conclusion based on historical and current published data. This is important both to 3D and to advanced packaging of “low-K” chips. ( I say current materials new material options become available all the time for instance see "Low K Material Family Introduced by SBA Materials" 09/07/2010 SST)

Again, bravo for this open and frank discussion of past errors in projection (see figure below).

The interconnect roadmap now accepts that “reduction of the ILD к value is slowing down because of problems with manufacturability. The poor mechanical strength and adhesion properties of lower-к materials are obstructing their incorporation. Delamination and damage during CMP are major problems at early stages of development, but for mass production, the hardness and adhesion properties needed to sustain the stress imposed during assembly and packaging must also be achieved. The difficulties associated with the integration of highly porous ultra-low-κ (к ≤2) materials are becoming clearer…..the slowdown of low-к in this edition, is further reflected by delaying low-к progress by one year in light of the actual pace of deployment of new technologies.”

They also conclude that despite the fact that “…spin-on dielectrics have the benefit of less dependence on precursors than CVD, that is, one tool can handle a variety of materials, including porogen. Various spin-on low-κ materials including porous materials have been studied. However, PECVD-SiCOH has been the dominant low-κ ILD film. Non-porous spin–on materials have not been used except in some special cases. Spin-on polymer and spin-on MSQ with к ≥ 2.4 are unlikely to be used for actual logic/memory devices, consequently spin-on materials, except porous-MSQ, have been deleted from the potential solutions figure”.

Finally, a formal roadmap admission that spin-on-organic ILD has been a total failure. What was the holy grail of chemical companies in the late 1990’s, and led to career ends for several major players, is at last labeled, what some of us knew all along – a dismal failure. Those who worked with me in those years know that I was a strong opponent of spending money to develop such materials and paid a price for my failure to support certain materials. A stronger man might be able to resist saying “I told you so” …..too bad I’m not a stronger man.

……..and now onto 3D in the 2009 Interconnect Roadmap

3D Definitions and Naming


For any technology to catch on we must all be using the same language to describe it.


The 3D roadmap writers ( which I’m sure included Arkalgud, Beyne, Ramm, Pozder, Scannell and Smith among others) have chosen to go with the IMEC 3D definition set which is modeled after the JISSO hierarchy levels.

3D-P and 3D-WLP seem pretty straight forward and I can see little resistance developing about their use. 3D-P meaning stack and wire bond technology that is firmly entrenched at all the OSATS and 3D –WLP based on WLP techniques performed after chip fabrication. Basically your TSV last, vias backside technology used in production today for CMOS image sensors.



I do have some resistance to use the next two however, not because they are incorrect, but rather because they will conflict with the near decade of 3D papers already out there. They use 3D –SIC to mean the stacking and interconnecting of large and medium circuit blocks and 3D-IC to mean 3D layer connection at the local interconnect level. I think most of us have been using 3D-IC (also seen as 3D IC or 3DIC) to mean what will now be called 3D-SIC. IFTLE will begrudgingly try to conform to the new acronyms (apologizing in advance for when I will surely slip up)


Always of interest are the ITRS tables projecting what requirements will be needed at a given point in time for a given technology. I have reproduced below the tables for 3D-WLP and 3D-SIC.

All-in all a much better agreement with reality than the 2007 report which I had problems with [see PFTLE 44 “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmap”,9/11/2008].

If these numbers are for first year of commercial shipment, then I find the 3D-SIC numbers a bit aggressive in terms of low end of the TSV pitch and high end of the AR. I think INTC 3 is a fair depiction of general technological capability and INTC 4 is representative of Bob Patti’s (Tezzaron) W, W2W technology.

One small general complaint about the 3D section would be the lack of references in this section of the report. For example the “Emerging Interconnect” section dealing with topics like carbon nanotubes has 93 references while the 3D section has a mere total of 5.

In the next IFTLE we will look at a look at 3D technology and other advanced packaging as seen by the Packaging and Interconnect Committee.

For all the latest of 3D technology and advanced packaging stay linked to Insights From the Leading Edge, IFTLE………………..