IFTLE 158 2013 ConFab part 2: Amkor and Siliconware

Finishing our look at the June 2013 ConFab packaging activities.

Amkor

Bob Lanzone, Sr VP of Engineering Solutions for Amkor, like the other OSATS sees smartphones and tablets driving the market moving forward.

 

If you ever wondered who the key players were in each of the mobile phone IC functions, Lanzone used this enlightening slide from  Gartner.

 



Amkor's update on Copper Pillar technology indicates an expected doubling in demand this year and continued expansion into “all flip chip products”.  



 

Their “TSV status” takes credit for being the first into production with TSMC and Xilinx.



 

Looking at the 2.5D TSV & Interposer Supply Chain they see:

• High End Products : Networking, Servers

- Silicon interposers ; < 2um L/S, < 15nsec latency, > 25k μbumps per die

           - Amkor is engaged with Foundries to deliver silicon interposers today

• Mid Range Products : Gaming, Graphics, HDTV, Adv. Tablets

 - Silicon or Glass interposers ; < 3um L/S, < 25nsec latency, ~10k μbumps/die

             - Not actively pursuing glass interposers yet as infrastructure still immature

• Lower Cost Products : Lower End Tablets, Smart Phones

 -  Silicon, Glass or Laminate interposer ; < 8um L/S, low resistance, ~2k μbumps

              - Must provide cost reduction path to enable this sector

              - Working with laminate supply chain to enable

They are targeting 2014 for their “possum” stacking as shown below:



 

 

 

Siliconware (SPIL)

In the presentation “The expanding Role of OSATS in the Era of System Integration”, Mike MA , VP of R&D for SPIL looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.



 

He discusses the two current business models for 2.5D which are the “foundry model” supported by TSMC and the “collaboration model “ supported by GF and UMC. He now adds a third model “the OSAT turnkey model which is now supported by TSMC.

SPIL is the first OSAT to propose this OSAT centric model where the interposer is fabricated by the OSAT who then assembles and tests modules made with chips from multiple sources.  The impediment to this route in the past has been the lack of OSAT capability to fabricate the fine pitch interposers which require dual damascene processing capability, which until now was only available in the foundries. SPIL has now  announced the equipment for fine pitch interposer capability (>2 layers, 0.4-3um metal line width and 0.5um TSV ) has been purchased and is in place.

Ma indicates that while the foundries are not happy with this SPIL proposal, their customers, especially their fabless customers have been very supportive.  He feels the inherent lower cost structure of  OSATS will have a positive impact on the 2.5/3D market which has been somewhat stagnant since the FPGA and memory product announcements in 2010.



 

SPIL also announced a wafer level fan out (WLFO) program on 370 x 470mm organic based panels which they feel is a potential low cost solution for those with lower density interposer requirements.

 

For all the latest in 3DIC and advanced packaging stay linked to IFTLE…………………..

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



IFTLE 157 ECTC part 3: SPIL Backside Reveal, Sematech & IMEC Protrusion,SUNY Binghamton on Cu-Cu Bonding

Continuing with our look at the 2013 ECTC.

Siliconware detailed the “Integration Challenges of TSV Backside Via Reveal Processing”.

After via formation, finished CMOS wafers or interposers are temporarily bonded to glass carriers. The TSV are ‘ revealed ‘ by Si back grinding and plasma etch steps, passivated with PECVD nitride, and CMP’ed to open the Cu pillar area. The via reveal processes must maintain acceptably low

TTV to allow subsequent bonding/stacking steps. Also the process temperature must be lower than the carrier bonding adhesives which is a particular challenge for the dielectric deposition step. The SPIL backside reveal process is shown below.

A major challenge of the via-reveal process is control the exposed copper TSV height, because incoming wafers to via reveal can have significant compounded variation, such as TSV depth uniformity, glass thickness uniformity, adhesive thickness uniformity and Silicon thickness uniformity after grind.

 SEMATECH and RPI reported on their studies on “Backside TSV protrusion induced by thermal shock and Thermal Cycling”

The TSVs used for this study were fabricated on 300mm wafers with a TSV height of ~50μm

and an aspect ratio of ~10:1. The front side of the TSV wafer is bonded face down on a handle wafer and  backside-thinned to reveal the TSV and metallized to form testing lines and pads. The cross section schematic below shows the structure.

 

Various combinations of thermal loads (RT -  200 C - 400 C) and ramp-up/cool-down rates (0.167 C/s to 25 C/s) are used for thermal shock and thermal cycling tests. No TSV protrusion is visible at 200 C or below, while larger TSV protrusions are observed at higher peak temperatures.The avg TSV protrusion height, collected from 108 single TSVs under 3 testing pads over each die, increases from 0.1μm at 250 C to about 0.5μm at 400 C.

 

 

 



 

The TSV protrusion varies significantly from TSV to TSV, resulting in big error bars. This is reportedly due to the grain boundaries in each TSV (particularly near the Cu testing pads) being very different from TSV to TSV, indicating that the key mechanism for the protrusion could be related to the Cu grain boundary diffusion.

SEM images of the TSVs reveal delamination is observed at the interface between the Cu TSV and the Cu testing pad on top of the TSV-1, while delamination between Cu TSV sidewall and oxide liner is found in TSV-2.

 

 

IMEC also reported on protrusion issues in their paper “Impact of Post Plating Anneal and TSV Dimensions on Cu Pumping”

When Cu-filled TSVs are exposed to high temperatures during BEOL processing, compressive stresses arise in the Cu TSV due to the large difference in coefficient of thermal expansion with the surrounding Si. These stresses  are partly relaxed by irreversible extrusion of the Cu, a phenomenon known as ‘Cu pumping’, which may damage  the BEOL layers on top of the TSV. In order to reduce the amount of Cu pumping during BEOL processing, a high temperature anneal step can be applied after TSV plating and before Cu CMP.

IMEC, who is generally given credit for offering an anneal solution  protrusion problem in 2011 has now  used optical profilometry to study residual Cu pumping in TSVs with different post-plating anneals and different TSV dimensions ( 5 x 50um vs 10 x 100um ). In total ~ 4000 TSVs were inspected. Within one sample the Cu pumping values show  an intrinsic large spread, therefore the distribution tail rather than the median is determining the impact on BEOL reliability. Lower pumping was found in TSVs annealed at higher temperatures and for longer times. The sinter conditions of 20 min at 420 °C were confirmed as optimal post-plating anneal conditions.. However, in order to effectively control the impact on BEOL reliability, development efforts should also be aimed at reducing the Cu pumping distribution width.



 

SUNY Binghamton and SEMATECH presented their work on the “Mechanism of Low Temp Cu-Cu Direct Bonding for 3D TSV Package Interconnect”.

While the solder-based approach for connecting chips to packages or chips to chips has become the industry standard for at least the first generation of 2.5/3D products, but the potential to significantly drive this approach to finer pitch interconnects is limited. The leading method for fine pitch chip-to-chip interconnects (pitch of 10 microns or less) is generally believed to be Cu-Cu direct bonding. In the direct bonding of Cu to Cu, the flatness of the surface on a small scale (~1 micron) or a large scale (wafer or die scale) and the chemical condition of the surface play important roles in the quality of the bond. Other factors such as the Cu grain size and grain orientation may also impact the quality of the Cu-Cu bond.

 Therefore, it is necessary to use a reducing gas to decompose the oxides. Forming gas, which is a mixture of H2 and N2, can provide such a reducing environment to decompose copper oxides effectively.  Prior attempts to surface passivate / clean including self-assembled monolayer passivation , plasma cleaning and chemical mechanical polishing with a formic acid clean all result in  improved bond quality as a result of the passivation and cleaning approaches used. The Bingham / Sematech group CMP’ed the copper in the presence of benztriazole which protects the copper surface during CMP, but does not prevent oxidation once the CMP is complete. The cleaned surfaces were then exposed t atmospheric conditions for varying times and reexamined by XPS (Xray photoelectron spectroscopy)

 Cu2O and CuO can observed on the clean Cu surface after a short atmosphere exposure (1 minute), while Cu(OH)2 and/or CuCO3 can be observed on the surface after longer exposures longer exposures (>30 minutes).

 Wafers were cleaned by Ar sputter cleaned (NA) or annealed at 200ºC in forming gas (FGA).  Both wafer pairs were bonded within minutes after cleaning by thermo-compression bonding with a force of 80 kN at 195°C for 5 minutes. Samples of NA and FGA wafers exposed to the atmosphere for 30 min and then examined by XPS showed both CuO and Cu2O but no Cu(OH)2 .

The  NA and FGA Bonded Wafers were characterized by CSAM looking for voiding. The image of the bond interface for the FGA wafers indicates  an absence of voids for almost the entire interface, whereas the image of the bond interface for the NA indicates voids throughout the interface. They attribute the better bonding for the FGA wafers to more effective Cu oxide removal by the forming gas anneal.

 For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………….



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C.



IFTLE 156 2013 ConFab part 1 Sony, IBM, TI, SCP

Those of you that are readers of SST know from the editorials and blogs of  Editor Pete Singer that the ConFab is  Solid State Technology's annual conference and networking event. This year, it was held in June 23-26 in Las Vegas.  The overall theme of this year’s conference is “Filling the fabs of the future,”

IFTLE  put together two sessions on packaging  which were jointly sponsored by IEEE CPMT and ConFab.

The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high density interposers to the industry. [see “Siliconware announces entrance into high density 2.5D interposer market”].

Sony CMOS Image Sensor 3D Stacking

Fellow bearded blogger Dick James of Chipworks, in his presentation “inside Todays Hot Products” showed some great X sections of the Sony IMX135 13 Mpixel CMOS Image sensor. One of the first stacked image sensors it consists of a 90nm back illuminated sensor bonded F2F with a 65nm image processor

 

IBM Orthogonal Scaling

Subu Iyer , IBM Fellow, lectured on his theme of “orthogonal scaling” . His premise is that classical silicon scaling is saturating and we need orthogonal approaches to “scale all aspects of the system including footprint and power”. Subu sees scaling continuing down to the 7nm node, but  “the cost per transistor has begun to saturate”

 

 

 

He predicts that the next component of Advanced System Integration will be 3D Integration:

- large interposer platform for heterogeneous integration    

 

- Die Stacking

               - stacking of logic die (high and moderate power) 

               - stacking of memory die (low power)

- Wafer level stacking

His example of stacked memory is the Micron IBM program on stacked memory:

 

 

TI Thins Down Packaging

Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G

 

Iyer points out that while Package families are  proliferating, each package type has a “sweet spot” combination of cost, performance, form factor and reliability, driven by:

•Cost

•Electrical speed, power distribution and noise immunity

•Power dissipation

•Thickness, weight, PCB area consumption

•Board level reliability (BLR, drop)

•Environmental reliability

•Technical maturity vs. risk in high-volume manufacturing

•Testability

•Compatibility with Si process

STATS

Anderson of STATSChipPAC  points to smartphones and tablets driving our industry right now.



 

 

For all the latest on 3DIC and Advanced Packaging stay linked to IFTLE.........



 

 

 

 

 

 

 

IFTLE 155 2013 IEEE ECTC Part 2 Temporary Bonding

Continuing our look at key presentations from the 2013 IEEE ECTC Conference.

IMEC and Brewer Science reported on the “Integration and Manufacturing Aspects of Moving from  Waferbond HT 10.10  to ZoneBOND in Temporary Wafer Bonding…”

 Temporary wafer bonding has become a key element in the emergence of 3D Stacked IC technologies. In the past approaches such as IMECS have relied on the “thermal slide process” to debond the thinned wafer from the carrier.  There was a desire to move away from this process for several reasons including:
(1) stresses that are generated can cause cracks in thinned wafers, especially those containing TSV.
(2) slide debond normally conducted > 200 C which accelerates solder diffusion .
(3) cannot slide debond if already on dicing frame since no dicing tapes can take temps > 200 C.

This led to the development of the ZoneBOND process which has been described previously [ See IFTLE 61 and IFTLE 90]

Integration Changes Required for the ZoneBOND process

In the standard process sequence edge trimming is done to the device wafer prior to temporary bonding. If this is done in the ZoneBOND process the find that adhesive is trapped in the trimmed region of the wafer and clogs the grinding wheel during backside thinning.

A new integration scheme is proposed where edge trimming occurs after the bonding step as shown below.

 

Debonding is performed at room temperature in a SUSS DB12T debonder. First, a wet edge preparation is required in order to eliminate the high adhesion area of the adhesive layer between the 2 substrates. Then, the thin device wafer still bonded to the carrier is laminated onto a dicing tape on frame. Next, the room temperature peel off debonding separates the thin wafer from the carrier while the thin wafer is still on tape and on frame. A final cleaning step on tape is performed to remove adhesive residues from the device wafer.

CEA Leti reported on their comparison between the  “WSS and ZoneBond Temporary Bonding Techniques…”

The ZoneBOND technique requires silicon carriers that are treated with an antistick layer with an edge exclusion to ensure the adhesion. Temporary glue can be deposited either on the device, either on the carrier. Bonding is achieved under elevated temperature and separation requires a specific soaking of the bonded pairs to preliminary remove the adhesive from the edges.

 

 



 

The WSS system requires transparent carriers as the temporary adhesive is cured after bonding by UV exposure. Separation is enabled by a laser exposure which modifies a sensitive layer (named LTHC for Light to Heat Conversion) that has been deposited before bonding on the carrier.

 

 

 



Pros and cons of the processes are given in the attached table.

 

For all the latest in 3DIC and advanced packaging stay linked to IFTLE................

 



 

 

 



IFTLE 154 ICEP part 2: Thinning Effects on DRAM memory retention and More

Continuing our look at the Osaka ICEP conference held in April 2013.

ASET and Tohoku Univ

ASET and Tohoku Univ reported on the effects of thinning on DRAM and CMOS device characteristics. Basically the thinner the chip becomes, the more likely it is that mechanical stress will alter the device characteristics and that ionic impurities will contaminate the transistors.

Perhaps most importantly they thinned a 65nm NMOS DRAM to 200 um by mechanical grinding and then further thinned down to 30um by stress free CMP. They then examined the data retention time of the chip vs thickness (see below) . Data retention of the 30um thick device was ½ of that of the 200um device !

 

DNP

Dai Nippon Printing and AIST have examined the fabrication of interposers on 300 mm wafers and attempted to reduce cost.

500um thick interposers with 50um diameter TSV were fabricated on 300 mm wafers, insulted with SiO2 (TEOS based PECVD), filled with ECD Cu and the Cu CMP’ed to remove overburden (50-100um). They note that it was “difficult to form void free TSV due to he high aspect ratio (10:1).  Backside RDL was done with PBO dielectric (8um deposited and 50% shrinkage). They conclude that this process flow eliminates the need for wafer support since the 500um thinned wafers can be directly processed without support.

 

ITRI

ITRI described their studies on the assembly of 3D stacked chip with 30um pitch microbump interconnects using both non conductive paste (NCP) and anisotropic conductive film (ACF).

The bump structure for NCP bonding is shown below. Cu/Ni/Sn solder micro bumps are connected to Cu/Ni/AU micro bumps. For ACF Cu/Ni/AU micro bumps are joined to Cu/Ni/Au micro bumps.



 





 

The NCP was an epoxy thermoset. Properties of NCP and ACF are shown below.  

 

 

The NCP assembled chip stack passed 1000 cycles of TCT and 1000 hrs of HTS without any failures. The ACF assembled stacks all failed after 85/85 testing for 100 hrs and showed 7% failure after 500 cycles of TCT.

 

ITRI also reported on the reliability performance of two capillary underfills with different Tg and CTE used for µbump bonding on a silicon interposer.

The 20 um pitch µbumps were composed of 5um Cu / 3um Ni / 5um Sn2.5Ag (solder cap). Thermo-compression bonding was used to interconnect the µbumps at 280 C for 15 sec and the gaps then filled by one of the two underfills. Their properties are shown in the table below.

 

Temp cycling data resulted in the Weibull plot shown below. The mean time to failure of underfill A (higher Tg) vs B was 20% higher.



 

 

Ishihara Sangyo Kaisha (ISK)

ISK described the development of oxidation resistant Cu nanoparticles (50nm). Cu ink was prepared and printed (13um thick). Thermal treatment [ 200 C for 60 min under N2 + O2 followed by 250 C for 60 min under N2 + H2] This thermal sequence “burns” off the organics and sinters the particles to form a 0.2um copper film with 0.5uΩ cm resistivity.

Osaka Univ

Osaka Univ reported that Cu to Cu joining can be accomplished using Cu nanoparticle paste (10-20nm particles in glycol protective solvent) They examined the shear strength of the joint vs thermal treatment atmosphere and temperature. The strongest bond (40 MPa) was achieved through 673 K bonding for 300 sec under 15MPa pressure with a N2/O2 atmosphere.

Tohoku Univ and Korea Institute of Industrial Tech

Tohoku Univ and Korea Institute of Industrial Tech studied the interfacial reaction between solder filled TSV and copper pillar bumps. Ti layer  (50 – 400nm thick) was used as barrier layer between solder and Cu pillar bump. Thermal aging for 500 hrs at 150 C was conducted and the interface examined. IMC thickness increased with aging time and as thickness of Ti increased the IMC thickness decreased.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…..

 

 

 



 

 

 

 

 

 

 

 



 



IFTLE 153 IMAPS DPC part 3 Leti, Dow, STATSChipPAC

Finishing up our look at the 2013 IMAPS Device Packaging Conference

Leti

Leti examined the reliability of die to wafer bonding using copper/tin interconnects.  Above 232 C tin rapidly reacts with copper to produce higher melting point intermetallic compounds.

 

They studied thermal cycling ,TC (500x -40 to +125 C) and high temp storage , HTS (84 hrs at +125 C) for both underfilled and non underfilled Cu/Sn joints and found that TC has a more pronounced negative effect on yield and electrical performance than HTS.

After thermal cycling one finds increased growth of the Cu3Sn layer and cracks at the Cu/Cu3Sn interface. Underfilling has a positive impact on yield and electrical performance.

Leti also addressed the thermal and mechanical challenges of 3DIC integration.

In terms of mechanical issues, everyone agrees that BOW is the problem. Potential solutions include:

- compensation layers on both sides to match stress.

- compliant interconnect

- increase interposer thickness

- control polymer encapsulation.

The following is an interesting plot that they use to make the point that a thicker substrate is better for mechanical stiffness. IFTLE thinks this is a bit of an over simplification since it depends on the modulus of the insulator layers and the encapsulation and their thicknesses. Certainly the general conclusion is correct. 

 

Dow Chemical

Dow Chemical and Fraunhoffer IZM presented new data on BCB based  temporary bonding adhesive. The process flow for temp bonding is shown below:

 

 

 

 

Wafers can be bonded at 80 C with a bond time of ca. 1 min. and subsequent oven curing at 210 C for 1 hour. They find no alignment shift after curing. Wafers show no voiding or delamination after 1 hr at 325 C indicating excellent stability for all backside processing.

Mechanical debonding at room temp needs no irradiation or chemical treatments to release the thinned wafer. The mechanical debond is reported to be “… residue free”.

If bumped first, one can coat twice  to build up greater than 80um of BCB. Mechanical peel off reportedly does not delaminate any bumps. Subsequent cleaning is done with IPA.

 

Dow has also developed a pre applied underfill materials set. We were shown 25um thick film roll that was 330mm wide.

 



Dow also gave an update on the new BCB XP 120201 a new low stress version of their positive tone, aqueous developable 6500 series. It has reported  cure temp less than 180 C and an elongation at break now greater than 25%. .

STATSChipPAC (SCP)

SCP, one of the acknowledged leaders in fan out WLP announced the use of a new organic dielectric which results in more robust mechanical performance and now allows the packages to pass -55 to +125 thermal cycling. They have gotten 11 x 11mm 28nm die in 14x14mm substrates on 0.4mm pitch to pass reliability.

 

 





For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………….

 



 



IFTLE 152 2013 IMAPS Device Packaging Conference part 2

Continuing with our coverage of the March IMAPS DPC.

TI

In his keynote presentation on semiconductor packaging trends Devan Iyer of TI showed  a great chart on package shrinkage through the years. We have moved from the 1.75mm SOIC to the picostar 2G at 0.075mm which they claim to be the thinnest package available for portable products and can be buried into PCB layers . 

 

 Iyer  also listed the following packaging challenges for materials and assembly.

 

APSTL

Dev  Gupta of APSTL  examined  “Stacked package with improved bandwidth and power efficiency” . His conclusions are  based on the assumption that 2.5/3D technology is still immature and high cost and not ready for adoption in consumer products like smart phones. He is a proponent of what he calls “super PoP” packages.

He points to the recent presentations by JEDEC which indicated that TSV based wide IO would be an option for 2015 but would find strong competition in LPDDR4. { For further discussion of this issue see IFTLE 134,  “SEMI 3D European Summit – Is the Wide IO Driver Dead ?” ]

 

Gupta claims that the issues for Pop arise from increased power loss due to parasitics in the package and that this can be cured by inserting “signal conditioning chips “ (442)



 

Nanium

Nanium announced that they were installing  30mm WL fan in technology (Spheron PBO technology from Flip Chip Int) to compliment their WL fan out technology already in place.

Corning

Corning discussed their 3D carrier glass substrates used in the wafer thinning process. 

They supply glass carriers for the 3M temp bond / debond process. Their fusion glass process results in surfaces with RMS 0.3nm; Ra 0.2 nm and Z range 4.2nm which is better than lapped and polished glass.



 

200 & 300 mm wafers cut out of a sheet. 450 will not be a problem and panels are ready when the industry becomes ready to use them.

They are using alumino-silicate glass (SGW3) to match CTE od Si from 0 – 300 C.  This CTE match keeps warpage very low. Corning pointed out that measuring TTV on these wafers is difficult and that reports in the literature of 1 um TTV are sometimes as far off as 5 um.

Recycling glass wafers depends on all process perameters, but in general they envision  15 recycles as doable.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….