Continuing
with our look at the 2013 ECTC.
Siliconware detailed the “Integration Challenges
of TSV Backside Via Reveal Processing”.
After via formation, finished CMOS wafers or interposers
are temporarily bonded to glass carriers. The TSV are ‘ revealed ‘ by Si back
grinding and plasma etch steps, passivated with PECVD nitride, and CMP’ed to
open the Cu pillar area. The via reveal processes must maintain acceptably low
TTV to allow subsequent bonding/stacking steps. Also the
process temperature must be lower than the carrier bonding adhesives which is a
particular challenge for the dielectric deposition step. The SPIL backside
reveal process is shown below.
A major challenge of the via-reveal process is control the exposed copper TSV height, because incoming wafers to via reveal can have significant compounded variation, such as TSV depth uniformity, glass thickness uniformity, adhesive thickness uniformity and Silicon thickness uniformity after grind.
The TSVs used for this study were fabricated on 300mm
wafers with a TSV height of ~50μm
and an aspect ratio of ~10:1. The front side of the TSV
wafer is bonded face down on a handle wafer and
backside-thinned to reveal the TSV and metallized to form testing lines
and pads. The cross section schematic below shows the structure.
Various
combinations of thermal loads (RT - 200
C - 400 C) and ramp-up/cool-down rates (0.167 C/s to 25 C/s) are used for
thermal shock and thermal cycling tests. No TSV protrusion is visible at 200 C
or below, while larger TSV protrusions are observed at higher peak
temperatures.The avg TSV protrusion height, collected from 108 single TSVs
under 3 testing pads over each die, increases from 0.1μm at 250 C to about 0.5μm at 400 C.
The TSV
protrusion varies significantly from TSV to TSV, resulting in big error bars.
This is reportedly due to the grain boundaries in each TSV (particularly near
the Cu testing pads) being very different from TSV to TSV, indicating that the
key mechanism for the protrusion could be related to the Cu grain boundary
diffusion.
SEM images of
the TSVs reveal delamination is observed at the interface between the Cu TSV
and the Cu testing pad on top of the TSV-1, while delamination between Cu TSV
sidewall and oxide liner is found in TSV-2.
IMEC also reported on protrusion issues in their paper
“Impact of Post Plating Anneal and TSV Dimensions on Cu Pumping”
When
Cu-filled TSVs are exposed to high temperatures during BEOL processing,
compressive stresses arise in the Cu TSV due to the large difference in
coefficient of thermal expansion with the surrounding Si. These stresses are partly relaxed by irreversible extrusion
of the Cu, a phenomenon known as ‘Cu pumping’, which may damage the BEOL layers on top of the TSV. In order
to reduce the amount of Cu pumping during BEOL processing, a high temperature
anneal step can be applied after TSV plating and before Cu CMP.
IMEC, who is
generally given credit for offering an anneal solution protrusion problem in 2011 has now used optical profilometry to study residual Cu
pumping in TSVs with different post-plating anneals and different TSV
dimensions ( 5 x 50um vs 10 x 100um ). In total ~ 4000 TSVs were inspected.
Within one sample the Cu pumping values show
an intrinsic large spread, therefore the distribution tail rather than
the median is determining the impact on BEOL reliability. Lower pumping was
found in TSVs annealed at higher temperatures and for longer times. The sinter
conditions of 20 min at 420 °C were confirmed as optimal post-plating anneal
conditions.. However, in order to effectively control the impact on BEOL
reliability, development efforts should also be aimed at reducing the Cu
pumping distribution width.
SUNY
Binghamton and SEMATECH presented their work on the
“Mechanism of Low Temp Cu-Cu Direct Bonding for 3D TSV Package Interconnect”.
While the solder-based approach for connecting chips to
packages or chips to chips has become the industry standard for at least the
first generation of 2.5/3D products, but the potential to significantly drive
this approach to finer pitch interconnects is limited. The leading method for
fine pitch chip-to-chip interconnects (pitch of 10 microns or less) is generally
believed to be Cu-Cu direct bonding. In the direct bonding of Cu to Cu, the
flatness of the surface on a small scale (~1 micron) or a large scale (wafer or
die scale) and the chemical condition of the surface play important roles in
the quality of the bond. Other factors such as the Cu grain size and grain
orientation may also impact the quality of the Cu-Cu bond.
The NA and FGA Bonded Wafers were characterized by CSAM
looking for voiding. The image of the bond interface for the FGA wafers
indicates an absence of voids for almost
the entire interface, whereas the image of the bond interface for the NA
indicates voids throughout the interface. They attribute the better bonding for
the FGA wafers to more effective Cu oxide removal by the forming gas anneal.
C.
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