Will Monolithic 3D IC Technology
become a real competitor to 3DIC with TSV ?
The language
of 3DIC is certainly a bit confusing. In the past I have made fun of EE Times reporters
confusing BE finfet technology with TSV based 3DIC. [ see IFTLE 62 "3D and Interposers – Nomenclature confusion; Equipment Market Shift to PkgingContinues" ].
There is also
confusion brewing concerning TSV based 3DIC and what can be called monolithic
3DIC.
Back end (BE)
3DIC with TSV is a parallel process where each layer or stratum is fabricated
with TSV separately and subsequently joined. Monolithic 3DIC is a front end (FE),
sequential process where a second layer of silicon is deposited or grown onto
the first finished chip and the transistor and interconnect processes are
repeated.
The issue
with the sequential process has always been the temperatures required to
deposit or grow a second crystalline layer of silicon on top of the IC. It is
difficult to overcome the 400°C process temperature limitation imposed by the
use of aluminum and copper IC interconnect
when creating the second layer of silicon and implanting and annealing
the second layer of transistors.
For instance
the early work of Akasaka-san at the LSI R and D Labs of Mitsubishi Electric
described the basic concept of monolithic 3DIC as shown below [link].
It was
clear nearly 30 years ago that “To fabricate 3-D IC successfully, a wafer temperature
during the crystallization should be kept low enough not to destroy the device
or not to change the device performance fabricated in the beneath layer”. They
proposed that the key was to “to control the thermal profile in the polysilicon
layer” and Akasaka proposed “..a laser or an electron beam recrystallization is
thought to be a suitable method due to their
effective
low process temperature”.
Certainly
laser annealing has come a long way since the first prognostications of Aksaka.
Will these advances allow monolithic 3DIC to compete with TSV based 3DIC ? Some say that sequential 3D technology can be much less complex and expensive to implement,...maybe we will be finding out soon.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………….
Zvi Or-bach
of Monolithic 3DIC is now proposing the use of smart-cut® for the formation of
the second strata (and not amorphous silicon crystallization) with shielding
layers to protect the first strata interconnect, as shown below [ link].
Will these advances allow monolithic 3DIC to compete with TSV based 3DIC ? Some say that sequential 3D technology can be much less complex and expensive to implement,...maybe we will be finding out soon.
CEA-Leti recently announced
an agreement with Qualcomm to assess the feasibility and the value of
sequential 3D technology [link]. The program between Leti and Qualcomm reportedly
“..will allow the critical assessment of
this technology in the context of practical applications, further evaluating
the potential impact of this sequential 3D technology for future
industrialization”.
In early January Taiwan's National Applied Research Laboratories
(NARL) said can use monolithic 3D-IC technology to make “super chips” [ link].They
reported that it “ enables 150 layers of
chips to fit in space once used to stack a mere two chips using traditional
technology while helping improve signal propagation speed and provide a higher
order of connectivity”.
[ IFTLE
note – “150 layers is likely the silliest marketing statement I have seen since IBM and 3M released the
headline claiming “3M and IBM today announced that the two companies plan to
jointly develop …. stacked silicon towers…..commercial microprocessors composed
of layers of up to 100 separate chips.” .[link]
At the recent
IEEE IEDM meeting Taiwan’s National Nano Device Laboratories described
fabricating a monolithic sub-50nm 3D
chip, which integrates high-speed logic and nonvolatile and SRAM memory. To
build the device layers, the researchers deposited amorphous silicon and
crystallized it with laser pulses. They then thinned and planarized the
silicon, enabling the fabrication of ultrathin, ultraflat devices. The
monolithic 3D architecture demonstrated 3-ps logic circuits, 1-T 500ns
nonvolatile memories and 6T SRAMs with low noise and small footprints.
Merck
to Purchase AZ Electronic Materials (AZEM)
Consolidation in the
microelectronics industry continued in Dec when Merck agreed to buy AZ Electronic Materials SA (AZEM) for $2.6 B. Merck which controls the liquid crystal
market for flat panel displays now becomes on the largest photoresist
suppliers.[link]
Intel
Invests in SBA Materials
Startup
Santa Barbara Materials (SBA Materials) with patented “Liquid Phase
Self Assembly” technology is a nano--‐structured,
advanced siloxane based approach to porous compositions that could have use in
electronics, optical and energy storage arenas. IFTLE has been keeping an eye on SBA for several years
since they appear to be the only SiO2 dielectric choice for Low K IC
chips that can actually deliver on sub 2.5 Dk [ see “Low-k dielectric familyintroduced by SBA Materials” and IFTLE 138,
“Foundry Intel; 300 mm Capacity; SBA Low-K Oxide”].
SBA has
recently closed a series B financing
round which included Intel Capital as one of the investors. [link] CEO Bill
Cook indicates that more will be coming on the strategic investor front “soon”.
2013 Semi Award to Xilinx
SEMI has announced that Xilinx is a recipient of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer “which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging” Liam Madden accepted the award on behalf of the Xilinx which includes Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young.
Semi stated that “Xilinx use of a silicon interposer in their packaging of advanced FPGA represents a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die…. While the elements of redistribution layers on silicon, TSVs, and microbumps were already available [they had not been combined commercially] to provide this high bandwidth, low power packaging solution.”
SEMI has announced that Xilinx is a recipient of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer “which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging” Liam Madden accepted the award on behalf of the Xilinx which includes Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young.
Semi stated that “Xilinx use of a silicon interposer in their packaging of advanced FPGA represents a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die…. While the elements of redistribution layers on silicon, TSVs, and microbumps were already available [they had not been combined commercially] to provide this high bandwidth, low power packaging solution.”
For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………….
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