The 2013 IEEE
IEDM was held in WDC the 2nd week of Dec. Lets take a look at some
of the key 3DIC presentations there.
Micron
Chamdrasekaran
addressed challenges in future memory manufacturing for both front end 3D NAND
and back end 3DIC stacking. He does not see any of the newer memory
technologies making inroads against conventional DRAM or NAND in the next
decade.
Micron
proposes that “..3D integration faces several equipment and fundamental
technology challenges. Bonding dicing and packaging equipment have not evolved
to the same level of control capability as front end equipment technologies.”
In terms of fundamental technologies they see challenges in thin wafer
handling, thermal budget management and stress constraints.
New
techniques will be required to test the silicon interposers with TSV and 3D
devices keeping test costs low. Ability
of probe technology to handle finer pitch TSV tips, eliminate probe created
scrub mark defects, and handling of thinned wafers are all viewed as significant
challenges.
3D stacking
also introduces intra die defects due to several processing steps, which needs
to be detected and understood. Thinned die and multiple materials with different
thermal expansion coefficients also create thermo-mechanical problems that can
lead to test and probe issues.
TSMC
Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.
Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60 GHz system in US is from 57-64 GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300 μm
LTCC and PCB
substrate are currently used for integration of mm-wave antenna with RF chip but
there are power consumption issues. The high power dissipation results from
interconnect losses from chip to antenna through bumps or balls. “Antenna-on-chip”
is other proposed solution to reduce the signal loss, but silicon is lossy and
degrades the antenna efficiency.
The TSMC antenna
structure is depicted in the figure below. It consists of two RDLs sandwiching mold
compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on
the top of MC and the other one is for feeding structure embedded in the
polymer on the bottom of MC as shown in the figure.
This FO-WLP array
antenna integrated technology has been approved for millimeter wave system
applications. High gain array antennas of 14.7 dBi, low-loss interconnects of
0.7 dB and small form factor of 10 × 10 × 0.5 mm3 can be achieved
with the technology. So called “InFO-WLP” is reported to be an excellent
technology for system scaling of low power millimeter wave applications on high-data-rate
wireless communication.
Comparison of
power savings, parasitics and system performance/size is shown below.
NC State
Paul Franzon presented
on applications and design styles for 3DIC. When comparing 2.5D interposers vs
3DIC stacking . While 3DIC technology offers a substantial advantage in interconnect
power efficiency and bandwidth density (effective wiring density * bit rate),
their thermal flux is higher, complicating cooling. On the other hand,
interposers add more cost than just TSV processing, which will keep them out of
lower cost markets such as mobile. Two big advantages for interposers are that
they reduce the need for power/ground feedthroughs and physical
standards. This was a significant barrier to the adoption of Wide IO but can be
overcome through adoption of appropriate standards.
ASET
because TSV revealing is unnecessary. The via-last TSV process
has two main advantages: first, modification of the BEOL process is unnecessary
and, second, reliability concerns such as the “copper extrusion (pop-up)
problem” do not arise.
ASET studied a process flow using the thinning after
bonding approach. This is the process used by Tezzaron [ see xx ] With this method, temporary bonding is not
necessary, so process cost should be reduced.
The process flow of thinning-after bonding is shown below
. First,
copper bumps embedded
with polymer are formed on three wafers . Co-planarization
of the copper/polymer surface by CMP is used to form a flat bonding surface.
The step height between the copper bump and polymer was kept to below 50 nm
across the entire wafer surfaces. The wafers (“LSI-wafer 1” and “Si-IP”) are
then subjected to face-to-face (F2F) bonding.
Copper-copper bonding was achieved by applying hydrogen-radical
cleaning. Next, the bonded wafer is subjected to wafer thinning and
backside-via-last TSV processes Total-thickness variation (TTV) of the thinned
wafer was kept to around 1.4 μm. A backside-via-last TSV was connected to
copper/low-k
interconnects. The diameter and length of the TSV were respectively
7 and 25 μm. After that the backside-via-last TSV processes, the bottom wafer
“LSI wafer 2” is directly bonded to the previously bonded wafers in
back-to-face (B2F) configuration. A three-layer-stacked CMOS wafer was
successfully fabricated by the above-described processes.
To maximize
interconnect resources, contact of the TSVs with the copper/low-k interconnects
should be restricted to the lowest interconnect level possible. Cross-sectional
SEM images of the stack is shown below.
Fabricated devices
exhibit high TSV yield of at least 99.2% and low TSV capacitance (about 40 fF).
The transmission performance of the TSVs is 15 Tbps/W. Copper/low-k damage is
reportedly negligible after via-last TSV formation. TSV-contact wiring needs
only two
interconnect levels. The estimated KOZ is up to 2 μm from
a TSV because of low silicon stress (less than 50 MPa).
Mechanical Stress Induced by TSVs
Cu diffusion
from backside surface of the surface of Si substrate is more significantly
influenced
as the
Si thickness is reduced. A dry polish (DP) treatment produced a superior
extrinsic gettering (EG) layer to Cu diffusion at the backside.
The
retention characteristics of DRAM cell are degraded depending on the reduction
of the chip thickness. The retention time of DRAM cell in the 20-μm thick chip
is dramatically shorted by approximately 40% compared to the 50-μm thick chip.
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