IFTLE 163 Consolidation, The Leading Edge, EMPC Grenoble part 1

Consolidation Continues

We have spoken about consolidation many times in IFTLE. Most recently in IFTLE 148, “The Future of Packaging: A Look From 50,000 Feet” we predicted significant consolidation for both equipment and materials suppliers.  To be honest this has been focused on the front end equipment suppliers buying up their back end brethren. What happened this week was even more significant.

The $29B merger of Applied Materials with fellow front end equipment supplier  Tokyo Electron was an all-stock merger, which, if allowed by the courts,  will create a global powerhouse in semiconductor and display manufacturing technology. The company will have a new name, dual headquarters in Tokyo and Santa Clara, a dual listing on the Tokyo Stock Exchange and NASDAQ, and will be incorporated in the Netherlands. Under the terms of the deal, AMAT shareholders will own 68% of the new company and TEL shareholders 32%. Tetsuro Higashi, chairman, president and CEO of TEL, will serve as chairman of the new company, while Gary Dickerson, president and CEO of AMAT, will serve as chief executive officer of the new company.

 As we said in IFTLE 148 it’s all about the economics. By cutting duplicated Research and development and sharing the same platforms, the companies expect to achieve $250 million in annualized run-rate operating synergies by the end of the first year, rising to $500 million in the third year.

We should not view this as “Fait accomplis” because I’m sure the antitrust paperwork is being filed as we speak by their remaining competitors.

The Leading Edge

When I started this blog as “Perspectives From the Leading Edge” back in 2008 in Semiconductor International, I noted that we would be focused on the leading edge  because “..that’s where the money is made”. Further evidence of that came from IC Insights last week when they provided the headline “Leading edge technology to be responsible for entire 2013 increase in pure-play foundry sales” [link]

It appears that 51% of TSMC’s revenue and 50% of GlobalFoundries’ sales in 2013 are expected to be from ≤45nm processing. 

In 2012, only TSMC, GlobalFoundries, and UMC had significant sales of ≤45nm technology.  In 2013, TSMC is expected to have about 4x the dollar volume sales at ≤45nm as compared to GlobalFoundries and about 12x the ≤45nm sales of UMC ($10.33 billion for TSMC, $2.53 billion for GlobalFoundries, and $0.89 billion for UMC).  In contrast, SMIC only entered initial production of its 45nm technology in early 2012, more than three years after TSMC first put its 45nm process into production and is forecast to sell only $0.22 billion of ≤45nm technology this year.  In fact, only 22% of UMC’s 2013 revenue and 11% of SMIC’s 2013 sales are forecast to come from devices having ≤45nm feature sizes, which is why their revenue per wafer is so low as compared to TSMC and GlobalFoundries.

 IC Insights contends that all of the increase in pure-play foundry sales in 2013 is expected to be due to ≤28nm feature size device sales. “ While the >28nm pure-play foundry market is expected to decline 3% in 2013,  leading-edge ≤28nm is forecast to triple this year.  Not only is essentially all the of pure-play foundry market growth forecast to come from leading-edge production, most of the profits that will be realized are also expected to come from the finer feature size sales”.

Despite continued rumors of process and yield problems in the 28nm TSMC fab, TSMC is forecast to have about $6.33 billion in sales of 28nm devices in 2013and as a result, TSMC is expected to hold a 78% share of the pure-play foundry industry’s $8.10 billion of ≤28nm sales this year.

EMPC Grenoble

The recent European Microelectronics Packaging Conference, EMPC, was held in Grenoble Fr. We will be taking a look at some of the key papers from the conference over the next few weeks.

IMEC

IMEC  reported on electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. They report on studies done to assess the effects induced by TSV, wafer thinning and stacking.

The Figure below shows measurements done for PFET transistors ( 2 channel lengths (50nm and 300nm) with TSV of 5um diameter). They conclude that the longer channel is more sensitive to TSV presence, i.e. at a distance of 5um from TSV center, they measure I_ON variation of 7% in the case of 300nm channel and 2.5% variation in case of 50nm channel. NFET transistors are less sensitive to TSV proximity. At a distance of 5um from TSV center, they measure a max I_ON variation of 2.5%. Similar to PFET, NFET transistors with longer channels are also more sensitive to TSV proximity.

No relevant change in the device drive current and therefore no major effect induced by the thinning or stacking processes.

 

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