At this weeks
GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive
theme appeared to be whether a change in substrate is required to lower overall
costs and help drive HVM (high volume
manufacturing) applications. Certainly conference chair Rao Tummala, industry
visionary whose name is synonomous with microelectronic packaging, feels the
time is right to take a serious look at glass interposers both for their
superior electrical performance and their promise of lower costs. The PB
substrate manufacturers are also taking a serious look at this market and proposing
that they can drive their technology to the required dimensions and electrical
performance, though many skeptics including IFTLE are taking a “show me”
attitude about these claims.
Status in Silicon
The Yole Developpement presentation pointed
out that while 2.5D silicon interposer technology was fully underway at TSMC and
GlobalFoundries, UMC and SPIL supposedly are near initiation, all of the
rumored “driver applications”, like the Apple A7, the next gen Qualcomm phone, the
Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next
generation Altera FPGA ( see discussion below) have been, at the very least,
postponed. While no one would openly reveal what the current and proposed
future costs are, it is believed that all of these postponements are due to
cost which certainly is not yet meeting the mobile phone requirements of less
than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e this is roughly $550 for a 300mm wafer of interposers).
While Yole
has identified at least 10 products moving towards commercialization, all of
them currently require so called high density interposers (i.e. 1um L/S and as
small as 10um TSV). Currently these dimensions can only be fabricated using front end dual
damascene type processing available only at silicon foundries and more recently
the OSAT, SPIL.
While Yole is
still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity
revenues including TSV etching, filling, RDL, bumping, wafer test & wafer
level assembly), these projections only hold if the current “postponed
applications” are quickly commercialized.
During the Amkor presentation Ron Huemoeller indicated
that lowering cost could come from elimination of backside RDL on the
interposers by arranging pin out on the top side high density interconnect.
Huemoeller
sees high end applications being dominated by silicon, mid end applications
like graphics possibly using glass and the low end applications (yet
unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being
adopted in 2015 and tablets and processors adopting interposer solutions the
following year.
In terms of
organic “interposers” he indicates that Shinko and Semco are in limited
sampling of 2/2 (L/S) and Kyocera 5/5.
He labels Unimicron as in “early development”
After making
the standard IFTE argument that 2.5/3DIC was needed to combat the costs of
continued scaling and that system level cost savings could pay for interposer costs,
Dave McCann of GlobalFoundries indicated that GF was achieving near 100% yields with
reticle sized interposers having 4 layers of high density interconnect.
McCann
predicted we would see voltage regulator function on future interposers. He
also described a program between Global
(chip and silicon interposer), Open-Silicon (design) , Cadence (EDA tools) and Amkor
(assembly and test), which produced a functional processor vehicle featuring
two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built
on a 65nm manufacturing flow. The program demonstrated first-time functionality of the
processor, interposer, substrate and the die-to-substrate assembly process. The
design tools, process design kit (PDK), design rules, and supply chain are now
in place for other activities.
What will be the Glass Interposer
Infrastructure ?
Inherently
most believe that all things being equal, glass should be a lower cost
interposer solution since it can be processed in large format. However, one
interesting question from the audience was “…why are silicon and glass wafer
the same price then ?”
Although the
data from experts like Professor Kim from KAIST
confirms that glass is a better electrical performance solution, especially for
Rf applications, the major issue is that a complete infrastructure is not yet
in place to manufacture such glass interposers.
The big 3
glass producers ( Corning, Asahi Glass
and Schott) have been listening to Tummala for several years now and all 3
are involved with his GaTech interposer consortium which has been promoting the
use of glass. They each have their own technologies for forming TSV, but the infrastructure
appears to stop there. While Corning’s Windsor Thomas said they are nearly
ready to ship rolls of glass containing TSV, the question expressed by many in the
audience was “ship to who ? ” Schott is in the same position.
Corning TSV
Asahi Glass
(AGC), however, appears to be a step ahead, having announced the formation of
Triton, to produce and deliver circuitized glass interposers (link). This
certainly will help AGC better understand the market and what the technology
limitations are.
Neither the “panel
of experts”, the speakers or the audience had a convincing argument as to
whether traditional flat panel LCD manufacturers or PCB houses would be better
at handling the metallization and singulation issues that still remain with
glass panels (or rolls). LCD manufacturers use aluminum, not copper and we are
told by Thomas of Corning “Have absolutely no interest in this technology at
all”. The PCB industry appears interested (certainly by their presence at this
meeting) but would have to change nearly every unit operation and material that
they currently use in order to meet the advanced requirements of 2.5D
interposers.
What can PCB based Interposers Deliver
PCB’s are of
course the first interposers, i.e most of the BGA substrates that exit today
are PCB technology. So really the question that is being asked is “ …can PCB
technology ever produce thin film silicon dimensions?”
Hu of Unimicron indicated that moving toward
2/2 (L/S) in polymeric PCB technology was doable but would require a move from
wet processing to dry processing, the use of stepper lithography, embedded
copper lines and a change of core
material to minimize warpage. Even if 2um lines and spaces were possible, this
would have to be done in a class 100 clean room (more cost !) and does not address
the TSV and catch pad dimension issue which really determines how many layers of
interconnect are needed. If materials are changed and a move to thin film processes
and equipment and facilities are needed, IFTLE questions whether costs will be
considerably lower.
Koizumi of Shinko showed data on a 200um glass core
PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) .
When diced such structures resulted in what they called “Se-wa-re” (loosely
translated back split) which was fracture through the glass core layer due to
the stresses built up on both sides of the core.
GIT Conclusions
Enough encouraging data was shown to reasonably
conclude that both glass and PCB should continue to be examined to fully
understand their ultimate capabilities and costs.
Altera 2.5D Postponed
For those of
you who haven’t noticed, the move of Altera to Intel to build FPGAs using its
14-nm FinFET process technology [link] basically
terminated the intentions of Altera to commercialize FPGAs using the TSMC CoWoS
process as previously disclosed [link]
This is certainly
another setback for 2.5D commercialization.
For all the
latest in 3DIC and advanced packaging stay linked to IFTLE……………………….
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