Nanium
Ricardo Gai, head of eWLB engineering at Nanium gave a
presentation on wafer level fan out packaging, FO WLP.
Nanium, headquartered in Portugal, is derived from the following bloodlines:
Nanium has been in 300mm HVM of FO WLP since Q3 2010 and has shipped more than 350MM packages . For a complete discussion of eWLB see IFTLE 124, “Statusand the Future of eWLB….”.
Process Challenges with eWLB:
●
Warpage - Warpage and shape changes
during processing; stiffness is a key parameter to control;
- Equipment modifications are
required to handle FO-WLP wafers - hardware – new end effectors and new chuck sealing
- software – upgrades for warpage handling
●
Die-Shift - In case of complex devices like (Multichip SiP), mask aligners are
not capable of overlay requirements and a stepper is required.
●
Multi-Layer RDL for multilayer RDL the overlay must be smaller than the die
shift. This also requires stepper technology.
●
Fine RDL Line Width / Space and Fine Ball Pitch - - better resist technology is
necessary to achieve L/S = 10/10
● Cost
Pressures
-
more die per carrier by using smaller edge exclusion zone
- larger substrate sizes
– 300mm and large panel processing to
reduce costs.
Future Challenges:
- thinner substrates will require
temp bonding and front side protection
GlobalFoundries
Jon Greenwood of GlobalFoundries
gave a presentation on 2.5/3D readiness for HVM.
Global Foundries is dedicated to
support the Collaborative Partner Model:
They are creating a supply chain where GF is responsible for
the wafer processing and backside integration (BSI) and assembly is owned by
the OSAT partners.
As we have discussed before [ see IFTLE 142, “GlobalFoundries2.5 / 3D at 20nm…” ] 2.5D interposer work is ongoing in Singapore and 3D
activity is in NY. In June 2013 they announced a certified set of design flows
for 2.5D interposers.
As
the next slide shows, by 2015 they hope to offer TSV “in all nodes”
Greenwood
announced that GF thinks their 2.5D and 3D packaging capabilities are proven
and their primary focus moving forward is yield and COO reduction.
Amkor
Ron Huemoeller Sr VP of Advanced Product Development at
Amkor presented their position on 3D/2.5D Market readiness.
Design capability status - established
- Mass production of optical sensors since 2008
- Worlds first fully integrated MCM TSV product started production in 2011
- System integrated architecture proven on many platforms such as
- multiple logic on Si interposers - logic + memory on SI interposers - memory / memory stack - memory / logic combination
Manfacturing Capability
- fine pitch Cu pillar in HVM
- wafer thinning equipment and infrastructure in place
- TSV etch equipment and infrastructure well established
- Backside passivation - equipment and infrastructure well established
- Backside bumping - equipment and infrastructure well established -
wafer support – equipment and infrastructure in place but still needs
improvement
- Assembly can be done chip-on-substrate, chip-on-wafer or
chip-on-chip
- more work is needed on testing memory prior to committing to package
stack.
Memory
- End customer chooses memory supplier (only primary memory
sources today)
- Receive as KGM on tape and reel
- receiving 2, 4 die stacks in wide IO format
Amkor now sees interposer use reaching “value markets” post
2015.
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