IFTLE 136 European 3D SEMI Summit part 3

Continuing our look at the SEMI 3D European Summit:

Oerlikon Systems

Oerlikon systems discussed PVD solutions for TSV metallization. Since sputter deposition is line-of-sight, it has been difficult for it to fill high AR features. Ionized PVD addresses this coverage in high AR issue, but significantly increases the equipment costs.

Highly ionized sputtering (HIS) is based on high power pulsed magnetron sputtering and reportedly has excellent directionality and film quality. It deposits at a higher rate that ionized PVD.  They showed the following coverage for TI barrier layer in 10:1 AR TSV...



and the following data for Cu seed layers:

IMEC

Eric Beyne of IMEC discussed the 3D technology maturation process and COO issues.

The std IMEC 3DIC TSV process has had 5 x 50 um TSV, but recently they have indicated that a more to 3um dia TSV may be warranted. One reason is that a reduction in the dia of the TSV correspondingly reduces the keep out zone (KOZ) requirements. 



Another interesting comparison was the thermal impact of Cu/Sn intermetallic bumps vs Cu-Cu bonds, where the direct copper-copper bonding shows a significant reduction in temperature.

IMEC assessment of the cost structure for a 10 x 100 um interposer TSV vs a std 5 x 50 TSV vs the proposed 3 x 50 TSV looks like this:



Amkor

Ron Huemoeller of Amkor addresses future packaging needs. He showed an interesting Prismark slide, which showed that smart phones and tablets will account for more than 50% of the Semi Ind growth through 2016.

In terms of interposers, Ron shared his views on interposer density vs application space. IFTLE has mentioned several times that the only interposer programs that have been announced are ones requiring high density interposers only available from foundries. Although this statement still holds true, Ron points to “ lower end smart phones and tablets” as potentially requiring interposers with less than 8 um l/s which could be fabricated by an OSAT RDL line. 

In terms of memory supply for 2.5/3D products, Ron lists on Elpida (Micron) and Hynix as currently supplying.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.



IFTLE 135 UMC/SCP Memory on Logic; SEMI Europe 3D Summit part 2

UMC/STATSChipPAC

UMC and STATS ChipPAC (SCP) have announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip. This was developed under open ecosystem collaboration using UMC’s foundry capability and STATS ChipPAC’s packaging capabilities. Representatives of UMC and SCP both declined to indicate where the memory came from, but did say that they were working with customers to commercialize this product.

Continuing our look at the European SEMI 3D Summit:

Xilinx

Suresh Ramalingam, Sr Dir of Adv. Packaging shared a nice slide on the CoWoS TSMC process being used to fab their Virtex-7 2000T FPGAs.

Cadence

Brandon Wang, Director 3D IC and Advanced Technology Product Management
for Cadence gave us the latest IBIS take on the costs incurred at the latest nodes,

and their short, medium and long term look at TSV application space.

SSEC
Laura Mauer of SSEC compared post grind TSV reveal options noting that KOH etches Si at 3-4X the reate of TMAH without touching SiO2 or copper.

SPTS

Dave Butler of SPTS also addressed the via reveal step. Dave contends that “standard” low temp TEOPS oxide is unstable over time absorbing water and showing increases in electrical leakage and refractive index changes. They recommend their “stable” LT TEOS oxide which they claim shows no drift in electrical properties, no changes in stress and no water absorption over time.

They also recommend using SiN as an etch stop layer to get up to 30% higher throughput.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE....

IFTLE 134 SEMI 3D European Summit – Is the Wide IO Driver Dead ?

SEMI European 3D Summit

SEMI Europe held their first European 3D TSV Summit in Grenoble in late January with a theme of “On the Road towards TSV Manufacturing”. Yann Guillou of Semi reports 320 attendees from 20 countries, 4 keynotes speakers, 22 invited speakers and 22 exhibitors were in attendance.

ST Micro

ST Micro presented their strategy for bringing 3D to manufacturing. An interesting slide compared yields with and without TSV.

 



They discussed digital / analog partitioning and memory on application processors as driving applications.

 

ST Ericsson

Kimmich of ST Ericsson discussed the application of 3D integration to smartphones. They were hyping fully depleated SOI technology (FD SOI) as being a faster, cooler and simpler solution.



 

 

He reported successful results from their WIOMING 3D application processor [ see IFTLE 86, “ 3D Headlines at the RTI 3D ASIP part Deux” and IFTLE 130 “3D-ASIP part 3,Wioming…”]

A cross section of the device is shown above ( STM wide IO memory on applications processor). The goal is to offer the same bandwidth as a quad channel 32 bit LPDDR2 interface but with half the power consumption. These are 10um dia TSV on 40 um pitch with AR = 8. The Cu pillar connections are 20um dia on 40 um pitch .  ST Ericsson reports there are still business issues concerning the wide IO business model.

An interesting chart on Memory Options shows wide IO bandwidth capability the same as LPDDR3 although the DDR memory takes a significant hit in power efficiency.



 

Another interesting conclusion is that PoP memory solutions offer better thermal performance since the thinned Si die in the 3D configuration result in poor lateral heat distribution.



 

 

In fact, Kimmich concludes that although 3D TSV technology appears ready for mass production, wide IO technology is not yet a fit for mainstream smartphones. LPDDR3 and LPDDR4 will be used in this application due to better thermal performance and lower cost.

GolbalFoundries

Greenwood of GF reitereated their recent theme of global collaboration enabling the global supply chain. Of interest was his slide outlining the production at various GF sites.



 

 

When it comes to 2.5/3D, GF is certainly well engaged across the world. The Fraunhoffer ASSID being on the same campus as Fab 1 Dresden is strategically aligned to GF collaboration. This co location insures “…an intensive and frequent knowledge exchange at the engineering level”.

 

AS IFTLE has reported previously see IFTLE 125, “2012 GaTech Interposer Conference, part I”, Fab 8 in NY is responsible for 3D solutions and Fab 7 in Singapore is responsible for 2.5D solutions.

Several 2.5D test structures were shown that were collaborations with Amkor.



 



 

For all the latest info on 3DIC and advanced packaging stay linked to IFTLE…………