IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013

Many of us can recall 2008 when Toshiba commercialized the first CMOS image sensor with TSV last /backside. We called these the first 3DIC products, when in reality they were only 1 layer devices.  More recently we have discussed Sony’s plans to release CMOS image sensors where the circuitry and sensors are fabricated on separate wafers and joined by TSV – i.e. true 3DIC structures. [ see IFTLE 112,”TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards;Sony shows off 3D stacked Image Sensors” and IFTLE  137, “http://electroiq.com/insights-from-leading-edge/2013/03/iftle-137-cmos-image-sensor-market-update/”

Somehow IFTLE missed detailing the actual product technology release of the Sony ISX014 (link)  at the ISSCC earlier in the year. This is important enough in terms of 3DIC product introductions that we will cover it now.

The Sony ISX014 8MP sensor features 1.12um pixels and integrated high speed ISP.The pixel layer and logic layer part are manufactured as separate chips and stacked by using TSVs. Previously the pixel and logic circuit of Sony's back side  illuminated (BSI) CMOS image sensor were formed during the same fabrication process. This is compared below.

Actual layers are shown below:

 

Using separate pixel and logic layers allows the use an optimal process technology for each separate layer. Sony fabricated the pixel chip and logic chip using 90nm and 65nm process technologies, respectively. Stacking the chips, reduced chip area by 30%, compared with the previous image sensor made using 90nm process technology.

TSVs are used connect the row drivers on the pixel chip with the row decoders on the logic chip and connect the comparators on the pixel chip and the counters on the logic chip. TSVs are formed in areas to reduce the influence of noise.  For example, comparators are arranged on the pixel chip, which can be manufactured by using Sony's matured process technology, rather than on the logic chip.

The stacked vs conventional technologies are compared below:

 

 

Since the logic chip can be manufactured at Si foundries, Sony does not have to invest in advanced logic process technologies.

 

Sony is in volume production of the new CMOS image sensor for its smartphone, other companies' tablet computers, etc. The size, pixel count and pixel pitch of the sensor are 1/4 inch, 8.08 million and 1.12μm, respectively. Characteristics of the CMOS device are shown below:



 

 

Sony has not disclosed details on TSV processing. The total number of TSVs is a few thousand. The following figure shows the stacked chips cross-section.The insulators of the upper and lower chips are attached together. It seems that TSVs are formed later to connect the circuit layers of the chips. IFTLE assumes they are using the Ziptronics oxide bonding technology that they licensed previously [ see IFTLE 65, “Samsung’s 32GB RDIMM DDR3, GLOBALFOUNDRIES Packaging Alliance, ZiptronixLicensing News”.

 

 



 

 

A recent cross section produced by chipworks helps us understand the interlayer connections done with 6um pitch TSV [link].

 

IFTLE would expect other CIS manufacturers to move in this direction shortly.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………….

Coming soon:

- An end of year update from Lester the Lightbulb         - more on IMAPS 2013

- more on the GIT Interposer Workshop                           - coverage of IWLPC                       

- more on IEEE 3DIC                                                              - coverage of RTI’s 3D ASIP                            

                               - Christmas coverage of Hannah and Madeline

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



IFTLE 171 Semicon Taiwan Part 3: Disco, Namics, Amkor

The last of our looks at September 2013s Semicon Taiwan.

Disco
Disco claims to have 73%of the edge trim business and 90% of the back grinding business.
Disco offers trimming before or after bonding as shown below. Trimming after bonding shows faster blade wear and lower throughput . Trimming before bonding requires additional cleaning before bonding.

Lowering the TTV (total thickness  variation) of temp bonding materials improves the  TTV of the thinned silicon wafer. One option is to surface planarize the temp bonding material.

 

Cleanliness during the grind and CMP operations can be handled by integrated grind / CMP / clean units.

 

Disco offers both Blade and Laser Dicing.

 

 

Namics

Namics gave an update on CUF underfills for 2.5/3DIC. The Namics roadmap for capillary underfill is shown below.

 

Only fine filler underfills can be used with TSV stacked packages. Higher filler loadings are needed to reduce filler CTE.

 

Higher thermal conductivity CUF can be made by increasing the filler content.

Vacuum assisted process or pressure assisted process can both be used to decrease voiding in CUF.

Amkor

Choon Lee of Amkor gave a presentation on “From Advanced Packaging to 2.5D/3D.

Interestingly  Lee predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.

Lee showed the following example of converting a silicon interposer to PCB.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…….

 

 

 

 

 

IFTLE 170 GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D

At this weeks GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive  HVM (high volume manufacturing) applications. Certainly conference chair Rao Tummala, industry visionary whose name is synonomous with microelectronic packaging, feels the time is right to take a serious look at glass interposers both for their superior electrical performance and their promise of lower costs. The PB substrate manufacturers are also taking a serious look at this market and proposing that they can drive their technology to the required dimensions and electrical performance, though many skeptics including IFTLE are taking a “show me” attitude about these claims.    

Status in Silicon

The Yole Developpement presentation pointed out that while 2.5D silicon interposer technology was fully underway at TSMC and GlobalFoundries, UMC and SPIL supposedly are near initiation, all of the rumored “driver applications”, like the Apple A7, the next gen Qualcomm phone, the Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next generation Altera FPGA ( see discussion below) have been, at the very least, postponed. While no one would openly reveal what the current and proposed future costs are, it is believed that all of these postponements are due to cost which certainly is not yet meeting the mobile phone requirements of less than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e this is roughly $550 for a 300mm wafer of interposers).

While Yole has identified at least 10 products moving towards commercialization, all of them currently require so called high density interposers (i.e. 1um L/S and as small as 10um TSV). Currently these dimensions  can only be fabricated using front end dual damascene type processing available only at silicon foundries and more recently the OSAT, SPIL.

While Yole is still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity revenues including TSV etching, filling, RDL, bumping, wafer test & wafer level assembly), these projections only hold if the current “postponed applications” are quickly commercialized.

 

During the Amkor presentation Ron Huemoeller indicated that lowering cost could come from elimination of backside RDL on the interposers by arranging pin out on the top side high density interconnect.

Huemoeller sees high end applications being dominated by silicon, mid end applications like graphics possibly using glass and the low end applications (yet unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being adopted in 2015 and tablets and processors adopting interposer solutions the following year.

In terms of organic “interposers” he indicates that Shinko and Semco are in limited sampling of  2/2 (L/S) and Kyocera 5/5. He labels Unimicron as in “early development”

After making the standard IFTE argument that 2.5/3DIC was needed to combat the costs of continued scaling and that system level cost savings could pay for interposer costs,  Dave McCann of GlobalFoundries indicated that GF was achieving near 100% yields with reticle sized interposers having 4 layers of high density interconnect.

McCann predicted we would see voltage regulator function on future interposers. He also described a program between Global (chip and silicon interposer), Open-Silicon (design) , Cadence (EDA tools) and Amkor (assembly and test), which produced a functional processor vehicle featuring two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built on a 65nm manufacturing flow. The program demonstrated first-time functionality of the processor, interposer, substrate and the die-to-substrate assembly process. The design tools, process design kit (PDK), design rules, and supply chain are now in place for other activities.

What will be the Glass Interposer Infrastructure ?  

Inherently most believe that all things being equal, glass should be a lower cost interposer solution since it can be processed in large format. However, one interesting question from the audience was “…why are silicon and glass wafer the same price then ?”

Although the data from experts like Professor Kim from KAIST confirms that glass is a better electrical performance solution, especially for Rf applications, the major issue is that a complete infrastructure is not yet in place to manufacture such glass interposers.

The big 3 glass producers ( Corning, Asahi Glass and Schott) have been listening to Tummala for several years now and all 3 are involved with his GaTech interposer consortium which has been promoting the use of glass. They each have their own technologies for forming TSV, but the infrastructure appears to stop there. While Corning’s Windsor Thomas said they are nearly ready to ship rolls of glass containing TSV, the question expressed by many in the audience was “ship to who ? ” Schott is in the same position.



 

 

Corning TSV

Asahi Glass (AGC), however, appears to be a step ahead, having announced the formation of Triton, to produce and deliver circuitized glass interposers (link). This certainly will help AGC better understand the market and what the technology limitations are.

Neither the “panel of experts”, the speakers or the audience had a convincing argument as to whether traditional flat panel LCD manufacturers or PCB houses would be better at handling the metallization and singulation issues that still remain with glass panels (or rolls). LCD manufacturers use aluminum, not copper and we are told by Thomas of Corning “Have absolutely no interest in this technology at all”. The PCB industry appears interested (certainly by their presence at this meeting) but would have to change nearly every unit operation and material that they currently use in order to meet the advanced requirements of 2.5D interposers.

What can PCB based Interposers Deliver

PCB’s are of course the first interposers, i.e most of the BGA substrates that exit today are PCB technology. So really the question that is being asked is “ …can PCB technology ever produce thin film silicon dimensions?”

Hu of Unimicron indicated that moving toward 2/2 (L/S) in polymeric PCB technology was doable but would require a move from wet processing to dry processing, the use of stepper lithography, embedded copper lines  and a change of core material to minimize warpage. Even if 2um lines and spaces were possible, this would have to be done in a class 100 clean room (more cost !) and does not address the TSV and catch pad dimension issue which really determines how many layers of interconnect are needed. If materials are changed and a move to thin film processes and equipment and facilities are needed, IFTLE questions whether costs will be considerably lower.



 

 

Koizumi of Shinko showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core.

GIT Conclusions

Enough encouraging data was shown to reasonably conclude that both glass and PCB should continue to be examined to fully understand their ultimate capabilities and costs.

 

Altera 2.5D Postponed

For those of you who haven’t noticed, the move of Altera to Intel to build FPGAs using its 14-nm FinFET process technology [link] basically terminated the intentions of Altera to commercialize FPGAs using the TSMC CoWoS process as previously disclosed [link]

This is certainly another setback for 2.5D commercialization.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………….



 

 

 

 

 

 

 

 

 

 

 

IFTLE 169 EMPC – Grenoble part 3: Fine Pitch RDL; Handling Ultra-thin Die; Backside Passivation as Stress Compensation

Leti / ST Micro – Interposer Fine Pitch RDL

Passive interposers redistribute the electrical lines from the attached upper dies down to the organic substrate through μPillars, RDL, TSVs and solder bumps, thus somehow acting as a pitch adapter between dies and substrate.

Backside RDL on a passive interposer can be created by either damascene integration or “conventional “ integration as shown in the figure below.

Damascene approach mainly consists in full wafer copper plating over etched trenches followed by a CMP, allowing to retrieve at the end, a fully planarized surface. This integration allows an easy access to sub-micron line/space widths but at a higher cost, mainly due to CMP steps.

 

Leti / ST Micro have investigated investigate the minimum pitch that could be achieved with the conventional approach. Under their conditions they were able to achieve 8um l/s with high uniformity and reproducibility.

BESI/IMEC – Handling Ultra-thin Die

The use of ultra thin die ( thickness less than 50um) requires specially designed handling solutions due to their fragility and flexibility.

BESI and IMEC have examined several tape types (UV vs thermal release), ejection systems, die size (5 x 5mm; 40um thick) and bump configurations.

 

They also examined both face up and face down to the wafer tape.

 

Their conclusions include: (1) proper dice/grind and stress relief needed to maximize die strength; (2) some UV tapes resulted in residues; (3) thermal release tapes gave larger process window; (4) stable and reliable picking of ultra-thin die can be achieved with throughputs greater than 3000 units per hour using several different hardware, maerial, process combinations.

 SPTS – Low Temp Via Reveal Passivation with Stress Compensation

2.5 and 3DIC wafers require backside processing including thinning to reveal the TSV, passivation, RDL and creation of copper pillar connections. Before the wafer reveal process CMOS devices are usually temp bonded to carriers (Si or glass) and thinned to ca. 50um. The temperature stability of the temporary bonding adhesive sets a limit on the upper temp of subsequent processing steps. The current goal for this temperature would be ca. 190 C.   

The backside passivation also serves to maintain the bow of the thinned wafers to a manageable level (ca. ~ 10mm) to allow subsequent processing steps. Full thickness 300mm wafers (770um) typically have incoming bow in the range of 100 – 200um. If thinned to  50um and released from the carrier the 300mm wafer would show a bow of several cm making them unprocessable and potentially lead to cracking after debond. Backside passivation stress can be tailored to compensate for the incoming wafer bow. CMOS cu/low-K wafers usually show tensile stress and thus backside stresses must be net tensile to compensate.

Compressively stressed SiN films generally give the best diffusion barrier properties. For the via reveal passivation stack compressive SiN with stress of – 100 MPa was used. 

SiO films deposited using TEOS based chemistry is tunable from -200 to +200 MPa, but are must be taken since tensile SiO has a limited thickness cracking threshold.

 



The final solution was to develop a 190 C SiN film with a tensile stress of +200 MPa and a cracking threshold of 7um (deposited onto compressive SiN barrier).

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………….

 Hope to see you all at this years RTI ASIP. It is the 10th anniversary of this very first meeting to be  focused on all aspects of 3DIC commercialization.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 



 



IFTLE 168 EMPC Part 2: FC Market; BLR of BoP WLCSPs; Chip Embedding; Temp Stability of Molding Compounds

Yole – FC Market & Tech Trends

Rozalia Beica, newly appointed CTO of Yole Developpement, examined the FC marketplace. The FC market is currently growing at CAGR of 19% as a result of expanded use in memory, consumer electronics and mobile phones. In 2012 bumping capacity of 14MM 300mm equiv. was in place accounting for 81% of all “mid end” capacity.

FC technology is being reshaped by the demand for Cu pillar bumping (CPB) and microbumps which are both quickly becoming mainstream. CPB is expected to show 35% CAGR over the period 2010 – 2018.

FC capacity is expected to grow in the next 5 years in response to demand from (1) 28nm CMOS application processor (APE) and baseband (BB) applications;(2) next gen DDR memory and (3) 2.5/3DIC.

 

                                                FC Bumping and CPB Forecast 2010 – 2018

 ASE – Board Level Reliability of BoP WLCSPs

There hsas been reduction of  the production cost for WLCSP packages for the past years. Today, many OSATs are working on further cost reduction with customized WLCSP package designs that are optimized for specific market needs.

For example, omitting the UBM layer on smaller WLCSP devices can reduce costs and may still meet the market requirement on package quality and reliability. Omitting the UBM requires 25% less process steps, from 4-mask process to 3-mask process.

ASE reports on the BLR performance of a 3-mask bump on polymer (BoP) WLCSP design vs  a 4-mask BoP WLCSP design for 0.4mm and 0.5mm ball pitch using  tin/silver/copper ( SAC) and SACNi (Ni doping) solders and reports on failure analysis.

 

     WLCSP (a) 4 mask process with UBM; (b) 3 mask process without UBM;  

(c) failure modes for 3 mask process

The polymer material can be polyimide (PI) or Polybenzobisoxazole (PBO) with thickness of  5um to 7.5um. In most BOP WLCSP packages, ASE states that PBO is the preferred material for better stress compliance, and hence better board level reliability.

For 3-mask WLCSP design, there is no UBM. The solder ball is directly attached to the redistribution layer, using polymer 2 to define the pad opening. Therefore, the electrolytic plating copper thickness for RDL needs to be sufficiently thick to avoid any problems due to Cu consumption during SnxCuy intermetallic (IMC) formation during thermal ageing. For these reasons the Cu RDL thickness is increased from 4um, on 4-mask WLCSP, to about 8um on the 3 mask process to ensure a reliable solder joint. the thickness of polymer-2 also needs to increase to 12um polymer-2 thickness to ensure line coverage. A 12um thick polymer-2 layer creates processing challenge for PI or PBO, and the thermal stress or residual stress after high temperature curing needs to be carefully controlled to guarantee the integrity of package structure.

After board level reliability test, failure analysis was performed to confirm the failure mode. The failure modes were classified as failed at PCB side Mode A, failed at component side Mode B and solder fracture Mode C. In the failure analysis, we found that BLR failure modes are governed by shear rate applied to the tested samples. High shear rate test, like drop test, tended to fail at the component side with IMC fracture (Mode B2) or residual solder on pad (Mode B3). But, for slow shear rate test, like temperature cycling test, the fail tended to occur at the solder joint (Mode C). They concluded that 3-mask the WLCSP does not change the failure mode in either temperature cycling test or drop test.

They conclude:

- BLR temperature cycling performance is governed by the WLCSP device size (DNP). The bigger the DNP, the worse temperature cycling lifetime. This was evident for both solder materials used in this study, even though the larger device has a larger solder joint size, and there was a larger difference between SAC405 devices than SACNi devices.

-  In general, the 3-mask WLCP has worse BLR performance than 4-mask WLCSP.

-  SACNi solder gives improved BLR Drop test performance (characteristic life, and first fails) for both 4-mask and 3-mask WLCSP devices.

-  They found the same failure mechanism and failure modes on 3-mask WLCSP as 4-mask WLCSP.

 Chip Embedding at IMS

 Ultra-thin chips  (less than 50 μm thick) can be assembled by either on flexible films; i.e. chip-on-foil technology or by embedding them inside the foil. Initial work by the Institute for Microelectronics Stuttgart (IMS CHIPS) dealt with attempts to glue attach Chipfilm dies onto flexible foil substrates. They have now described research with < 20μm thickness die with a two polymer (BCB and PI) ultra-thin chip imbedding approach.

Polymers used for embedding should be flexible and at the same time strong enough to keep the chip firmly embedded. To achieve an optimal solution for the desired process IMS used a combination of polymers where BCB serves as the embedding polymer for ultra-thin chips and the PI as the  reinforcement polymer. The X sectional structure  is shown below.



 

Two Polymer Embedding of Ultra-thin Chips

The PI reinforcement layer provides strong yet bendable reinforcement for the entire chip stack. The BCB embedding polymer provides excellent electrical properties, low moisture absorption, compatibility with the interconnect metals and fine pitch patterning compatibility.  The process flow is shown below. An initial “adhesion lowering layer” is initially coated on the wafer to allow for package removal once the process is complete.

 

Ultra Thin Chip Embedding Process Flow

The figure below compares the warpage of the free standing 4.6 x 4.6mm 20um thick chip to the chip once bonded to the lower BCB layer of the structure.

 

NXP- High Temp Capabilities of Epoxy Molding Compounds

Packaging for automotive and other high temp applications and for GaN and SiC high temp technologies requires  packaging be able to withstand high temperatures. Epoxy Molding compounds (EMC) will therefore be subjected to steadily higher ambient temperatures, possibly reaching their intrinsic limitations. Currently,  few materials have been qualified to withstand ambient temperatures of greater than 175C.

NXP studied the degradation mechanism of three types of epoxy molding compounds (A): OCN-based, Tg greater than 150°C, (B): Biphenyl-based, Tg approx. 120°C and (C): Multiaromatic, Tg approx130°C.

When an EMC is exposed to air (oxygen) at high temperature, two competing chemical reactions take place. During oxidation, oxygen gets incorporated into the polymer chains and the resultant groups (e.g. carbonyl groups) can react with hydrogen atoms from neighboring chains, leading to an increase in cross-linking density of the EMC. Oxidation also leads to chain scission, where smaller more volatile molecules are liberated into the air. Both reactions lead to chemical shrinkage in the polymer. Thermal ageing in air leads to an increase in intrinsic stress (due to shrinkage) and a decrease in strength for the oxidized layer. When the intrinsic stress exceeds the strength of the EMC cracks form on the surface.

It is expected that some key thermomechanical properties will change after ageing, the main changes will probably take place only in the oxidized layer.

A number of (thermo)- mechanical properties were measured like the glass transition temperature (Tg), Storage Modulus (E’), Loss modulus (E”), CTE below and above Tg (CTE1 and CTE2) and the flexural strength. All of these properties degrade with oxidation .

Even before the onset of external cracks in the compound, it has been shown that ageing leads to a relatively porous and “open” oxidized layer.

Class C (Multi-aromatic) have the most stable performance demonstrating  that a high Tg does not necessarily imply higher thermal stability.

CMST (U Gent/IMEC) – Parylene as a Diffusion Barrier

CMST and co-workers have studied the use of Parylene [ poly(p-xylyene)] as a barrier material for biocompatible implants. The packaging of implantable devices needs to be miniaturized as well as the devices. The barrier layers should be hermetic , i.e provide a bidirectional diffusion barrier . Parylene C and N are prone to oxidation at temperatures above 70 C. Testing showed   limited water vapor barrier protection, adhesion issues with certain surfaces and limited copper corrosion (although only after 170 hrs). Copper diffusion is observed through a Parylene barrier layer . They conclude that Parylene  in combination with other layers might be a better solution. [IFTLE offers that NO Polymer is a hermetic barrier and as such should not be used as the main source of hermeticity for implantable devices. ]

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………….

 

 



IFTLE 167 IARPA Trusted Integrated Chips program (TIC); The Apple A7

Halloween

In the US we are approaching Oct 31, the day for pumpkins and witches. Hannah and Madeline wish all IFTLE readers a Happy Halloween.

 

IARPA Trusted Integrated Chips

At the IEEE 3DIC in San Francisco Dan Radack of IDA [Institute of Defense Analysis] recently gave an update on the  IARPA trusted Integrated Chip Program known as TIC

Background

From 19996 – 2006 the IC Fab at Ft Meade was used to fabricate ICs required for Govt. programs. It was mothballed 5-6 years ago. From 2003 to present the Govt. has used so called “trusted foundries” but they found that they were not able to provide everything that the Govt. needed.

With all of the top foundries now situated outside the US or owned by non US entities, there was a need for a new way of insuring secure state of the art chip procurement. This certainly dovetailed with the interest in cyber security i.e. how to prevent counterfeits and the vision of needing more-than-Moore technology (i.e. sensors in a 3D chip stack) in the future.

Trusted Integrated Chips program TIC

In the summer of 2011 The Intelligence Advanced Research Projects Activity (IARPA) announced its  Trusted Integrated Chips program. TIC features what IARPA calls "split-manufacturing," where fabrication of new chips is divided into Front-End-of-Line (FEOL) manufacturing consisting of transistor layers to be fabricated by offshore state-of-the-art” foundries lines and Back-End-of-Line (BEOL) development that would be fabricated by trusted U.S. facilities.

In this approach, the design intention is not disclosed to the FEOL fabricators. "FEOL circuit fabrication to the point of only the first metallization layer can be used to obfuscate the design and performance of an integrated chip thereby protecting the intellectual property of the designer. Alternately, circuit obfuscation can be realized through a chip integration strategy whereby only partial circuits are fabricated on any single chip but when integrated with other chips or wafers in a US manufacturing or packaging facility, a complete safe and secure circuit or system can be realized," IARPA stated.

According to IARPA, the vision of the TIC Program is to ensure that the United States can:

• obtain the highest performance possible in integrated circuits

• obtain near 100% assurance that designs are safe and secure -- not compromised with malicious circuitry

• ensure security of designs, capability, and performance while simultaneously protecting intellectual property

• realize secure systems combining advanced CMOS with other high value chips.

The TIC program is examining  a number of split-manufacturing concepts in the following areas:

• Mixed Signal                       • Photonics-CMOS                       • MEMS-CMOS

• Power-CMOS                      • RF CMOS                                  • Memory-CMOS

• Josephson Junctions-CMOS                    • Other systems integrated with CMOS

The five-year program was divided into three phases with the development and demonstration of split-manufacturing starting at the 130 nm technology node in Phase 1. It is anticipated that the TIC Program performers will scale the development of their capabilities to the 22 nm node at the end of a five-year period in Phase 3.

Sandia National Laboratories was selected to coordinate the FEOL and BEOL processing with Multi-Project Wafer runs carried out by the University of Southern California/Information Sciences Institute (USC/ISI) using their MOSIS service.

6 organizations did design of CMOS circuits in the MPW multi project wafer . Global foundries performed the front end work and  IBM Burlington fabricated the interconnect layers . Each of the 6 designers then capped the structure with their heterogeneous layer .

NGAS, Cornell, Lucent, Raytheon Vision systems , CMU, Stanford

Raytheon capped with focal plane array for vision system

Carnegie Mellon – cap with piezoelectric MEMS containing digital, analog and smart SRAM

Bell Labs / Lucent – cap in photonics layer

Northrup Grumman – InP mm wave circuits

Cornell – FPGA with ultrasonic comm. Cap

Stanford - cap with materials and ReRam (resistive RAM)

The program is now moving to 65 nm. The move to 28nm will be June or 2014

 Details on the Apple A7

The Apple A7 is a PoP 64-bit SoC designed by Apple.  It first appeared in the iPhone 5S, which was introduced in September 2013. Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor, the Apple A6. The A7 is a 64-bit 1.3GHz dual-core CPU coupled with what’s believed to be a Power VR G6430 GPU. The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm² in size.

 



Fellow blogger Dick  James from Chipworks has sent the first shots of the PoP processor. He comments that  “”It looks as though there s some degree of bowing in the top package, and there is an interface layer between the two packages. ….Another surprise is silver wire in the Elpida DRAM package..the pitch of the TMV (through mold via) between the top and bottom packages is 0.35mm. Ball pitch on the base is 0.4mm. There are 3 rows of TMVs for a total of 456. Ball count on the base is 34 x 38 = 1292”

Cross section of the A7 is shown below.

 



 

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………………………………….