We have been talking about the JEDEC wide IO DRAM standards for a few years. [see IFTLE 19, "Semicon Taiwan 3D Forum Part 2"]
Wide I/O mobile DRAM using 3D stacking with TSV provides "double the bandwidth at the same power, or can cut power in half at the same bandwidth" compared to LPDDR2 and LPDDR3. It is reportedly "particularly suited for applications requiring increased memory bandwidth up to 17GB/second, such as 3D gaming, HD video and user multitasking."
Click on any of the images below to enlarge them.
Well, the spec is finally finished and JESD229 Wide I/O Single Data Rate (SDR) can be downloaded from the JEDEC website [link]
Wide I/O mobile DRAM enables 3D stacking with TSV interconnects and memory chips directly stacked upon a System on a Chip (SoC).
Wide I/O mobile DRAM enables 3D stacking with TSV interconnects and memory chips directly stacked upon a System on a Chip (SoC).
The standard defines features, functionalities, AC and DC characteristics, and ball/signal assignments. The specification employs "LPDDR2-like" commands and timing parameters. The 512-bit memory interface has four independent 128 bits wide channels each operating at clock speeds to 266 MHz. resulting in a total bandwidth of 17 Gb/s for wide I/O SDRAMs (4.26 Gb/s/channel). The specification supports as many as four memory banks per channel, allowing die stacking of up to four wide I/O SDRAM die. The specification calls for 1.2V signal levels.
The specification also standardizes:
- Boundary scan testing (Boundary scan logic is integrated into the die for contact and I/O testing, providing full test coverage for contacts, drivers and receivers.)
- Post-assembly DRAM test. (DRAM can be tested separately from the logic chip it's packaged with.)
- Mechanical layout of the chip-to-chip interface.
- Memory thermal sensor locations for DRAM, to provide reliable operation given thermal gradients introduced by logic chips.
JESD229 does not control the bonding configuration between the memory and logic chips – i.e. side-by-side with interposer, or stacked memory on top of logic.
The next generation of this Wide I/O SDRAM specification, already underway, will reportedly deliver eight times the performance and support 2.5D assembly.
The JEDEC committee expects wide IO memory to be in mass production by 2014.
The specification also standardizes:
- Boundary scan testing (Boundary scan logic is integrated into the die for contact and I/O testing, providing full test coverage for contacts, drivers and receivers.)
- Post-assembly DRAM test. (DRAM can be tested separately from the logic chip it's packaged with.)
- Mechanical layout of the chip-to-chip interface.
- Memory thermal sensor locations for DRAM, to provide reliable operation given thermal gradients introduced by logic chips.
JESD229 does not control the bonding configuration between the memory and logic chips – i.e. side-by-side with interposer, or stacked memory on top of logic.
The next generation of this Wide I/O SDRAM specification, already underway, will reportedly deliver eight times the performance and support 2.5D assembly.
The JEDEC committee expects wide IO memory to be in mass production by 2014.
Elpida Starts Sample Shipments of wide IO Mobile DRAM
In late December Elpida announced that it has begun sample shipments of 4-gigabit Wide IO Mobile DRAM which will deliver increased performance and lower power consumption, aiming these products at the smartphone and tablet device markets.
By using x512-bit, a data width that is more than 10 times larger than the width for existing DRAMs, they enable a data transfer rate of 12.8 gigabytes per second (GB/s) per chip while operating at a low speed of 200MHz. The reduced DRAM speed results in approximately 50% less power consumption compared with DDR2 Mobile RAM (LPDDR2), currently the leading DRAM choice for mobile devices, configured at the same transfer rate. Elpida plans to begin volume production in 2012. Future plans are to develop two-layer 8-gigabit and four-layer 16-gigabit high-density packages for addition to the company's product line-up.[link]
Elpida Facing Global Memory Consolidation
There are only 6 significant DRAM suppliers left in the world: Samsung, Hynix, Micron, Elpida, Nanya, and Powerchip. Elpida, born of the consolidation of the DRAM businesses of NEC, Mitsubishi, and Hitachi in 1999, is the last remaining Japanese DRAM manufacturer. "Elpida" is Greek for "hope" and like the Greek economy, Elpida, the Japanese memory company, appears to be out of hope and financially on its last leg. The major problem is that many of Elpida's competitors have NAND to fall back on when the DRAM market is doing badly, but Elpida has only DRAM to keep itself alive.
IFTLE views Elpida as one of the bright stars of 3DIC. Last fall IFTLE discussed the Business Week proposal that memory company consolidation was on the horizon [see IFTLE 69, "Cell Phones and Memory Consolidation"], how Elpida's financial outlook was grim and how Toshiba was the likely merger candidate. Digitimes reports that Elpida and Toshiba are in talks to merge their business operations. The merger is being "pushed" by the Japanese government, which reportedly wants Japan to keep its DRAM technology ownership on shore.
[see Digitimes Jan 3rd, 2012 "Elpida and Toshiba Reportedly in Integration Talks"]
Others are pointing towards talks between Elpida, Micron, and Nanya. Last week Reuters reported that Elpida is in talks to merge with U.S. firm Micron Technology and Taiwan's Nanya Technology. Elpida said it would not comment on rumors and speculation. [link]
Micron has a 10-year agreement with Nanya (until 2018) to co-develop new DRAM chip technology. The two also run contract DRAM maker Inotera Memory via a joint venture. Nanya has posted losses for seven consecutive quarters but has been kept going by funds from its parent, the Formosa petrochemical group.
Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs
At the IC Packaging Technology Expo at NEPCON Japan in Tokyo, Renesas announced that it will apply TSV technology to its mobile SoCs so that they will support Wide I/O DRAM starting with mobile phone products. The DRAM will be stacked on the back of the SoC via 1,200 microbumps. The company plans to contract out the production of advanced SoCs to a silicon foundry as well as the production of TSV. [link]
IBM Comments on 22 nm and Beyond
Subu Iyer, IBM fellow, noticed that I have been using the IC consolidation slide (below ) shown by Handel Jones of Int Business Strategies (IBS) at the Semi ISS meeting in 2010. [see PFTLE 121, "IC Consolidation, Node Scaling and 3DIC"]
For all the latest on 3D IC and advanced packaging stay linked to IFTLE.....................
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