The TechXSpot “Challenges and Solutions for 40nm and Beyond” was put together by Rich Rice of ASE and Tom Gregorich of Media Tek. Jim Walker of Gartner took a look at the macro trends effecting our industry including packaging. Walker proposes the following :
- between the 45nm and 8nm nodes, logic fab costs will double to $10 billion.
- only four companies will be able to follow Moore’s law by 2018
- the annual number of new fabs built will fall by 60% between 2011 and 2015
- by 2015 foundries will account for ~ 1/3 of the value of all semiconductors compared with ~ ¼ today
- by 2012, over 50% of packaging/test (SATS) will be outsourced
- by 2015 more than $30 billion in annual R and D expense will be saved by collaborative R and D.
Gartners estimation of total capacity availability by node and year is shown below followed by the fact that the finer feature chips are the ones driving packaging advances. Walker pointed out that between 1980 and 2010 the number of different packages available on the market has increased from 30 to more than 2200 !
The TechXSpot session 3D in the deep submicron era was led by Jie Xue, Cisco Systems and Gamal Rafai-Ahmed, AMD .
Eric Beyne of IMEC addressed the integration challenges for 3D-TSV with advanced devices.
Beyne pointed out that the M1 metal layers “above” the TSV consist of very narrow, high aspect ratio lines which require very flat surfaces: low dishing of Cu TSV CMP. The ULK dielectric layers in lower metal layers are of reduced strength which requires stable mechanical properties in the TSV i..e quire optimized post-plating annealing conditions to avoid copper protrusion. Semiconductor devices are very strain-sensitive. Strain is actively used to increase the mobility in the nMOS and pMOS FET channels. The stress induced by the Cu-TSVs may cause variability among devices. The use of higher stress in the device channels reduces the impact of small variations due to TSV’s. The strain in the Si substrates will impact planar devices differently than FINFET devices which are somewhat “decoupled from the substrate”.
To reduce the impact of TSV stress on devices, a keep-outzone is defined around the TSV structure. For advanced nodes, reducing this KOZ to a minimum becomes more important. The maximum stress induced in the Si by the TSV is in first order independent of the TSV diameter. The stress levels in the Si are proportional to (ØTSV/r)2 , with r the distance to TSV center, thus scaling down the diameter of the TSV by x reduces the “effective TSV area” (TSV+KOZ) by x4 ! [As we have noted mnany times in IFTLE, the smaller the TSV (diameter and AR), the better]Jon Greenwood of GlobalFoundries addressed backside integration and supply chain challenges.
When comparing 2.5 vs 3D integration Greenwood pointed out the following:
2.5D Integration
- For high performance applications, interposer option provides a thermal solution for near memory integration
- TSV technology is required to enable Si interposer
- Enables early TSV adoption
- Bridges design readiness, TSV impact and CPI concerns on device
- Typical interposer at 100 um thick allows time for back side and thin wafer handling processes to mature (increased system level yield)
3D Integration
- TSV middle technology is integrated into foundry process flows and node development
- Quickly becoming low power and mobile centric due to thermal management concerns
- Small form factor, high bandwidth applications
- TSV design and layout is critical to device performance and reliability
- Final device thickness typically at 50 um
- Additional yield concerns associated with thin wafer handling
They offer the following as what they view is becoming the standard TSV and backside processing flow.
In terms of supply chain they envision the foundry plus vs the OSAT plus vs the third party models as shown below where the manufacturing solution, reliability and warranty ownership is in the hands of the foundry, the OSAT or the 3rd party respectively. Its probably pertinent to insert at this point that the Xilinx program choose to have TSMC manufacture and FC the interposer and thus chose option #1.
Finally GF points out that while the substrate industry is stable and reliable, interposer delivery is a complete unknown.
GF concludes with the following thoughts:
- An integrated supply chain that offers customers yield accountability and competitive pricing needs to emerge
- Interposer model needs to follow the organic BGA supply chain progression from the early
1990’s to today
- Japan Centric growing to Worldwide Supply Chain with multiple HVM suppliers located
throughout Asia
-Significant cost reduction and competitive pricing evolution –i.e. over 90% cost reduction vs
today’s pricingspan>
- Substantial advancements in technology such as thickness reduction and warpage control, laser
vias, build up technology.
Ron Huemoeller of Amkor offered the following roadmap for silicon interposer products. While Amkor sees many TSV based products requiring an interposer, they see a severely constrained supply chain which is negatively impacting product proliferation.
For all the latest on 3D integration and advanced packaging stay linked to IFTLE…………………….
No comments:
Post a Comment