IFTLE 62 3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues

Some of you might remember a  late 1970s comic routine called "Raymond J. Johnson Jr" The character (shown at left) becomes annoyed when addressed as "Mr. Johnson" and exclaims  "My name is Raymond J. Johnson, Jr...now you can call me Ray, or you can call me J, or you can call me Johnny, or you can call me Sonny, or you can call me Junior; or you can call me Ray J, or you can call me RJ, or you can call me RJJ, or you can call me RJJ Jr but you don't hasta call me Mr. Johnson!"


Lots of equivalent names for the same person. Sometimes that happens in science and sometimes the exact opposite happens where lots of different things are all known by the same name - for instance 3D.

3D Confusion

At the recent Suss Workshop at Semicon West, I started of my 3D IC status lecture by pointing out the confusion occurring in the trade press about the term "3D." Below is a copy of the slide that I used. The culmination for me was the report released by the Taiwan trade development council July 5 with the catchy headline "TSMC may beat Intel to 3D chips." With a title like that this piece was widely picked up by the trade press and reprinted dozens of times on blogs and web pages by that evening. The example that I gave on the slide is EE Times (because it is the most prestigious of the lot) who appropriately referenced the original source (which may I say many others did not do) . In this haste to get material out to "the readership," no one appeared to have read the article to see that the original report was comparing apples to oranges or in this case TSMC 3D IC with TSV to Intel's announced finFET 3D IC transistor structures [ see IFTLE 50 "Words of Wisdom"]. I'm sure the trade development council authors, simply didn’t know the technical difference but the "copy cats," those who cut/paste and reprinted ...well they either also lacked the technical acumen to know the difference or simply didn't read it. EE Times corrected the story on July 11, curiously the same day the blog "SemiAccurate" lambasted them for their reporting [link]
When it comes to 3D be careful that you understand what you're reading about and don't always trust that the author has the knowledge or took the time to do the same. 



Silicon Interposers, 2.5 D or Silicon BGA

Looking back over the development of what is now commonly known as "silicon interposers" or "2.5D" as ASE's CTO Ho-Ming Tong has been calling them [see IFTLE 18, "The 3D IC Forum at 2010 Semicon Taiwan"] long time IFTLE (and PFTLE) readers are aware that I was not initially enamoured by silicon interposers due to my past experiences in "MCM-D" technology and was calling them silicon BGAs for awhile.[ see PFTLE 79, "Experience or Prejudice? Si Interposers Using TSV"] My views moderated with time as it became clear that there were strong drivers for Si interposers, this time around [ see PFTLE 109, "You Cannot Resist an Idea Whose Time has Come"]

The other day I decided to google "silicon ball grid array" and come up with a patent issued to old friend Dave Palmer, recently of Sandia. To be exact we are talking USP 6,052,287 filed in Dec of 1997 and issued in April of 2000 which gives it another 6 years of life. If you're in the business of making or using such interposers, you might want to give this patent a look !

Others point to the IBM patent  3,343,256 (1964) "Methods of Making Through connections in Semiconductor Wafers" and contest the validity of the Sandia patent. Only a legal battle will truly tell !

Cannon latest to enter packaging market.

With the number of players decreasing with each succeeding generation of scaling [ see PFTLE 121 "IC Consolidation, Node Scaling and 3D IC"] it is only logical that front end IC equipment vendors would be looking at the IC packaging market as an area into which they can expand.

In  April 2009 , PFTLE openly proposed that Applied appeared to be positioning to become  a "one stop shop" for those interested in 3D IC (see PFTLE, "Samsung 3D 'Roadmap' That Isn't").  In June of 2010 I added Novellus to that list as they announced a series of products aimed at the wafer level packaging and 3D IC with TSV markets [ see IFTLE 3   "....on Finding the Beef and Finally Addressing 3-D IC"]

The latest equipment supplier joining the group is Cannon who  made its first foray into the semiconductor back-end packaging equipment market with a lithography tool for through silicon via (TSV) and bumping.   Canon modified their  front-end tool series to accommodate the thicker resist films used by TSV and bump structures.  The system's projection lens optics expose 52 x 34 mm, compared with the 26 x 33 mm area exposed by front-end tools.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE............