IFTLE 96 A New Concept for a 3DIC Conference; Granddaughter Update

In the past IFTLE has ranted about how every technical conference on the face of the planet wanting  a piece of the 3D integration pie and how that is propagating severe redundancy in the presentations that are being given.  Paying $500 + travel expenses for a conference that gives you 15 3D presentations when you have already seen 12 of them under slightly modified titles can be upsetting. Going to a conference that gives you 1 session of  3DIC presentations and you’ve seen all 5 of them is even worse.  I don’t blame the presenters,  because I know they are being begged by the session chairs to submit their presentations even if they admit that they have nothing new to say.

Having said that, I must admit I was intrigued by the concept of the new conference “Connect in 3D” being sponsored by Yole Developpement this coming  fall ( Oct 31^st / Nov 1^st). For those of you who haven’t seen the advertising blurb try this link [link]

The concept originated with Brian Perkins of Highliner Events (yes that would be Jeff Perkins brother – isn’t nepotism great).  While many conferences try to set up their schedule so that the attendees can have “quality networking time”  Brian’s concept is to  have a conference that is basically all networking complete with terms like “speed dating”.  Will it work for a technical area like ours ?

IFTLE decided to throw some questions Brian and Jeff’s way so we can all get a better understanding about how this works.

IFTLE: Brian How did this “connect” program come about ? Has it been used in other technical venues and if so how has it worked.

BP: The real value of a conference is no longer the presentations, keynote addresses, or even white-papers. It is the decision-makers and influencers who attend—and the networking and collaboration  that occurs between them at the event—that are truly high-value. Networking is the Holy Grail of event value, and our Collaboration Summits^SM are designed to deliver the maximum networking opportunities in a variety of pre-scheduled, formal and informal formats with a minimum of ‘pre-packaged’ content. Yole has used the technique for a MEMS event, I’ll let Jeff address how he felt that went.

  JP: We launched our first event with Highliner last year targeting the MEMS inertial sensor space. Attendees at  the inaugural “MEMS in Motion” event really embraced the format.  As a technical crowd, they “got it” very quickly, everyone used the software tools to the max and respected every meeting time limit – making the absolute most of their time.  Attendees gave us a 100% satisfaction rating. This event design is an iterative and evolving process. These second edition Collaboration Summits have been revised based on feedback and observations made during the first event. We will continue to respond to the market as it dictates.

IFTLE: Will attendance be capped by total or by company ?

JP: We would like to see no more than 200 participants. At sometime we might also consider capping the number of participants from a single company. The value proposition being more companies participating is better.

IFTLE: If I have read the material correctly it looks like two types of meeting are set up. Some by the attendee and some by a computer which matches up attendees randomly. Is that correct? How does this work?

BP:   The bulk of the meetings are scheduled by the attendees themselves.  Attendees request, accept and or decline meetings with other attendees.  These will be 20-minute meetings with delegates of their choice, scheduled through the DealCenter online platform or at kiosks during the event. Private tables are setup for conference attendees to meet with the person(s) they made appointments with through the DealCenter. Confirmed meetings will be assigned a table number in the Connect in 3D meeting area.  In addition, there is a session where there is “speed dating” pre-arranged meetings which we will talk about in a few minutes….

JP: The DealCenter will open in September. Registered attendees will receive instructions in September via email when the DealCenter opens. All meeting planning is done through the DealCenter platform and every registered attendee will be able to see and request meetings with all other registered attendees. To be clear though - no contact information outside of the DealCenter contact point is ever made available unless users voluntarily provide it through their own meeting invitations or sent messages. So DealCenter is a temporary networking tool, setup for each event, allowing initial contact to be made, but any expansion of that contact is entirely up to you.

IFTLE: So all the attendees will be listed and I can privately sign up for 1 on 1 meeting with any of them before I get to the meeting. Those meetings are locked in – correct ?

BP: Remember the whole concept is about choice, so when I request a meeting with you, you have three options, you can accept the meeting, you can accept the meeting but suggest a different time, or you can decline the meeting. If you accept the meeting that is locked into our respective schedules.

IFTLE: What are the chances that the person I really want to meet will get booked up and I wont get to talk to him/her ? 

JP: It is entirely possible that the person you want to meet will be booked up for the 20-minute meetings, particularly if you wait until the last minute to register for the conference early bird registration really means something in this style event! However, all is not lost if they are booked - there is the possibility you will end up with a 10-minute speed dating meeting on the first day. Also there are all of the classic informal opportunities to meet: at the meals, we have extended coffee breaks and receptions. We actually enhance the ability to meet people by starting out the meeting with personal introductions. One of the key components to these events is the opening session introductions: so right after breakfast on the first day all of the participants gather in the plenary session room. We give a brief description of how the day will run, and then we begin the individual introductions.  It allows everyone to put a face with a name. If there is someone you really want to meet, you will know who they are and what they look like in the first 2 hours. You don’t have to wander around all day trying to read name badges.

 IFTLE: So how does the speed dating part work ?

BP: One of the important parts of any gathering of business professionals is the random connections that occur by serendipity. Our Meet the Market ( speed dating) meetings are designed to enhance that serendipity. These meetings will be set by the DealCenter program software a few days before the event. We want to be sure we have the maximum number of participants available to insure we capture everyone. The system will randomly pair attendees with other attendees screening for one meeting per individual from a given company and screening out anyone with whom you have already scheduled a 20-minute meeting.

IFTLE: What if speed dating assigns me to meet with a competitor, do I have to have those meetings ?

JP: The speed dating session is really about going with the flow.  We issue individual “date cards” minutes before the Meet the Market session starts and you go to each and every meeting, regardless of any sentiments you may have.  These meetings are 10 minutes – long enough to know if there is need to meet again, but not so long to make you uncomfortable.  At MEMS in Motion, even competitors that got paired up commented that they actually made a useful connection - serendipity indeed.   

 IFTLE: So what is the proportion of prepared materials (plenary presentations by experts / panel discussions) vs scheduled 20 min meetings vs speed dating over the two days ?

 BP : It breaks out to be just about 1/3 each  plus all the informal networking time at meals, breaks and receptions.  If you add in this informal time the breakdown is about 25% each

IFTLE : So to sum up, this is a conference which focuses on relationship building  through 2 days of networking in Palm Springs where you can get to have direct 1:1 meetings with people you have been wanting to meet ?

JP: In today’s world we are all too busy, the real point here is to make enough of a connection so that folks will pick up the phone when you call or open and reply to an email you send.

Update on the Girls

On the way to the IMAPS  Device Pkging Conf. stopped off in TX for the weekend to see how Hannah and Maddie  were doing. Ends up it was Rodeo weekend in Houston. Trust me you have never been to a rodeo till you’ve attended one in TX.  For those of you who do not understand why the Texas football team are known as the “longhorns” ... Now you do !

For all the latest in 3DIC and advanced packaging stay linked to IFTLE....................

IFTLE 95 3DIC – Time Flies When You're Having Fun; Further Details on the Micron HMC , Equipment Suppliers Continue Consolidation, EVG Temp Adhesive Open Platform

Time Flies When You're Having Fun with 3DIC

Seems like yesterday that the packaging world was hearing that Fujitsu, Toshiba, NEC, Oki, Renesas and others had formed a pre-competative consortium under the Association of Super Advanced Electronics Technologies  to study direct connecting of chips with through silicon vias (TSV). It seems like yesterday but it was 1999, 13 years ago.  

In Feb 2005 my first article on the topic “Future IC’s Going Vertical” was published in Semiconductor International predicting that the industry would eventually have to move in this direction. A short month later, March 2005 I felt like a prophet when a TSV based 3D stacking approach was described by Intel’s Justin Rattner (todays CTO) at the Spring Developer Forum, with statements like “...stacked wafers and stacked dies using thru-silicon vias are showing promise in meeting the memory bandwidth challenge.”

A year later, in April 2006 headlines from Soeul read “... Samsung has developed a new "3D" package, which reduces space requirements and increases performance capabilities of today's multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007” Samsung announced that its new wafer-level processed stack package (WSP) rather than using wire-bonding .... micron-sized holes that penetrate through the silicon vertically to connect circuits directly - TSV. According to Samsung the technology would enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. The announced that the technology would enter mass production in 2007, for NAND Flash packages initially. And that they planned to use WSP for server DRAM stack packages sometime down the road.

A year later, in April of 2007, the headlines were “ IBM has announced that they're relatively close to going commercial with a "through silicon via" (TSV) technology that will enable them to create high-bandwidth connections between two or more chips in a stacked packaging format." The big news about IBM's design is that the company intends to start shipping product samples based on this technology in the second half of this year, with full production coming in 2008. "Looks as if TSV will be here faster than anyone previously thought."

Now, thirteen years later ASET is in its 3rd incarnation “the Dream Chip program” , it is obvious that DRAM will be stacked before NAND flash hopefully in HVM by 2013 (not 2007) , IBM has announced a major memory program with Micron (though not in 2008) and we are still awaiting any word of commercialization from Intel. Certainly it’s fair to say that this is taking a bit longer than we all thought, even those of us who were trying to be ultra conservative.

Micon / IBM  HMC – further details

IFTLE has been sent a few messages asking for further details on the Hybrid memory cube production.

Micron has announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer. Micron will be doing the assembly of the layers at a yet to be disclosed location. For now we can assume they are doing the initial production in Boise. For our initial discussions on this technology see IFTLE 74, “The Micron Memory Cube consortium”.

The technology described by M. G. Farooq of IBM last December at the IEEE IEDM [ see IFTLE 82 “3DIC at the 2011 IEDM...”] is the technology being used to create the logic layer in the HMC stack (blue layer).

(Click on any of the pictures to enlarge them)

As noted in IFTLE 82, TSVs are integrated at “fatwire” (upper level metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD). TSV of less than 100 µm depth were etched with near vertical sidewalls at a minimum pitch of 50 µm. An example of this is shown below. It is believed that the Micron logic layers  are being done in SOI technology.

The logic layer for the HMC parts will be manufactured at IBM's advanced semiconductor fab in East Fishkill, N.Y., using the company's 32nm, high-K metal gate process technology [link]

Chipworks has concluded that “ it appears that the TSVs are annular. Once the lower metal / dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100 µm into the substrate, with a minimum pitch of 50 µm. After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP’d off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.” [link]

TEL acquires Nexx

Tokyo Electron Limited (TEL) has acquired semiconductor packaging equipment supplier NEXX. Nexx advanced deposition equipment, including electrochemical deposition (ECD) and physical vapor deposition (PVD) tools will be added to the TEL line of products aimed at back end packaging applications and 3DIC.


Long time readers know that this has been a theme identified by IFTLE [ see PFTLE 41, “ 3D Integration Stays Hot at Semicon West” or PFTLE 107 "3D News:Applied/Semitool, TSMC, Ziptronix”


Looks a lot like the front end heavy weights Applied, LAM and TEL are going to buy up all the pieces they need to become the 3 heavyweights in packaging and 3D. Consolidation will continue because with fewer and fewer players moving to 22 nm and beyond packaging is a natural evolution for some of these big front end equipment vendors.

Shin-Etsu Joins EVG Temp Adhesives open platform

Shin-Etsu’s adhesives will be entering qualification trials on EVG’s EZR (Edge Zone Release) and EZD (Edge Zone Debond) modules, which support the new ZoneBOND room temperature debonding process. Shin-Etsu is the first participant to announce for the program since its inception late last fall [ see IFTLE 76, “ Adv Pkging at IMAPS 2011: recent 3D Announcements”.

EVG’s ZoneBOND temporary bond / debond  solutions and open materials platform include:  the use of silicon, glass and other carriers; compatibility with existing, field-proven adhesive platforms; and the ability to debond at room temperature with virtually no vertical force being applied to the device wafer.  To support grinding and backside processing at high temperatures and to allow for low-force carrier separation, the concept defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone.  For further description of the technology see IFTLE 90 "Highlights from the IEEE 3DIC 2012 Japan" and refs therein.  

For all the latest on 3DIC and advanced packaging stay linked to IFTLE..................

IFTLE 94 Experts Discuss Interposer Infrastrucrure at IMAPS Device Packaging Conference

IFTLE brought together a  panel of manufacturers, users and market specialists at the 2012 IMAPS Device Packaging Conference in Fort McDowell AZ to discuss the Evolving 2.5D / 3D Infrastructure. [ Douglas Yu, Sr Director of front end and back end technology development for TSMC; Jonathon Greenwood, Director of Packaging R and D at GlobalFoundries;  Remi Yu, Deputy Division Director of UMC]memory suppliers [Nick Kim, VP of future electronic packaging technologies at Hynix] assembly houses [ Rich Rice, Sr VP of sales for ASE and Ron Huemoeller, VP of Advanced 3D interconnect at Amkor] users [Matt Nowak, Sr Director of Engineering at Qualcomm] and Market specialists [ Jan Vardaman, President of TechSearch Inc].

(Click on any of the images below to enlarge them)

       [l to r] Doug Yu [TSMC], Garrou [IFTLE],Huemoeller [Amkor], Vardaman [TechSearch],

Greenwood [GlobalFoundries], Yu [UMC], Kim [Hynix], Nowak [Qualcomm], Rice [ASE]

When asked whether 2.5/ 3D TSV technology has been narrowed down to copper TSV middle from IDM or foundries and some vias last backside all the panelists agreed with this conclusion. When asked about standard TSV dimensions, the foundry and OSAT representatives all agreed that 5-8 µm  on 50 µm thick Si looks like it has become the standardized offering that many of their customers are expressing interest in. When it came to interposers, they similarly all gave the nod to 100 µm thick interposers with ~ 10 um diameter TSV. 

Sourcing Interposers

A significant portion of the panels time was spent discussing current and future interposer sourcing. Assuming the attributes of “fine”vs “coarse” interposers as defined in the table below, the question becomes “where will these interposers be coming from” and “what will they be used for” ? 

So far announcements from Xilinx and Semtech indicate that they will both be using “fine pitch” interposers i.e fabricated by ~65 nm dual damascene [DD] CMOS processing by TSMC and IBM respectively. Altera and Nvida have also announced similar high density interposers for future use as have other graphics chip makers.

While all the OSATs have RDL technology capable of fabricating “coarse” interposers so far none of the major players [ ASE, Amkor, SCP, SPIL] have announced that they are entering the interposer business.

While all of the current roadmaps point to 2012-2014 as being the date for initiation of mass production for 2.5/3D products one must now ask where is the interposer production to meet this demand. If these lines are not in place now, is it easonable to think that products using them be qualified and in mass production within the next 24 months ?

During his conference presentation Amkors Huemoeller indicated that they would not be manufacturing interposers and their search of the industry for sources  indicated that only 3 players were close to being ready to deliver interposers that wee useful to Amkor, namely TSMC, UMC and GlobalFoundries.

 While glass panels and even possibly advanced laminates presented interesting possibilities for low cost future products, Amkor’s perspective is that  they are in the earliest stages of R&D.

All 3 of the foundry panelists indicated that they will be commercializing fine featured interposers although as we stated only TSMC and IBM had announced small volume product production has been initiated.

When asked about rumors circulating that OSATS are looking to put equipment in place to manufacture DD “fine pitch“ interposers, both Amkor and ASE indicated that they had no plans to do so.

IFTLE concludes that despite significant “industry chatter” the only programs that can afford interposers, so far, are programs that require the density or other attributes provided by fine featured interposers which can only be provided today by foundries /3D active IDMs. While we can anticipate that there might be products in the future that can be designed to take advantage of “coarse” interposers, and some of the initial fine interposer activities such as memory + logic + graphics chip applications might be able to migrate to coarse interposers as they become available, we will, initially at least, be limited by the availability and cost of foundry supplied interposers. 

The Evolving Infrastructure

TSMC reconfirmed  that they will provide full 2.5 / 3D service including chip design and fabrication, stacking and packaging [ see “2.5D announcements at the Global Interposer Techconference” and “TSMC repeats call for foundry-centric 2.5/3D industry” ]

TSMCs Yu indicated that they have made their thoughts clear in the past few months and it can be found clearly delineated on their web page. During his plenary lecture Yu once again indicated that fabrication of chips on interposers was not as easy as making prototypes makes it look and they strongly favored controlling and being responsible for the full process.

When asked about supplying memory needs, Yu indicated that they would also handle that by having partnerships in place to supply the required memory although these partners were not identified.

When asked for their positions, UMC and Global Foundries indicated a preference to work under the open ecosystem model where chips from various vendors could be stacked and assembled by OSAT partners.

When asked how the current economic issues surrounding Elpida was affecting the UMC/Elpida/PTI partnership, UMCs Remi Yu responded that this was only one engagement that they had in place for 2.5/3D and that they were moving forward with others.

Amkor’s Huemoeller indicated that foundries would be supplying interposers and they [ the OSATS] would be assembling them.

 ASE agreed short term but indicated that longer term they envisioned a broad “pie” with space for several types of players. ASE envisions future applications where coarse interposers would find their niche and be an important part of the technology base

Both of the OSATS, as would be expected, favored the open ecosystem model where chips from various suppliers would be assembled at the OSATS. 

Qualcomm reiterated a position that they have expressed in the past which is that interposers would add substantial cost to 3D stacking and as such probably would not be a broadly accepted solution for low cost mobile products

TSMCs Yu responded that indeed the addition of an interposer added cost to  the overall component, but that “...this [2.5D] solution also offers cost savings by reuse of IP and separating digital and analog circuitry and allowing partitioning of costly SoC “ and that this in fact could make it the lowest cost solution..

When Hynix was asked whether they would be offering memory stacks containing TSV as have been already announced by Samsung, Micron and Elpida Hynix Kim responded that he expects “2 and 4 chip memory stacks with TSV to be in mass production in 2013”

When the panel was asked with the wide IO memory standard is now in place. what other standards were needed quickly Nowak of Qualcomm indicated that the upcoming Semi handling and transport standards were needed and noted that standardization was also needed in the ESD area and  standardization in the “design exchange formats” where he feels Si2 is taking the lead.

When asked for their opinion on the current status of design tools all 3 of the foundries indicated that current design tools are adequate to move forward. Qualcomm’s Nowak offered that logic on logic design tools were still lacking.

In terms of test strategies UMC would like to see some better standardization in the test area while Yu of TSMC drew a chuckle from the crowd when he noted that test needed to be minimized. Similarly, on the assembly front Rice indicated that ASE is having to test “everything” till the yields are up and Amkor quickly concurred.

Focusing on the first generation of 2.5/3D  stacking interconnect all accepted that this will be done with Cu/Sn eutectic by reflow or thermo-compression bonding.   When asked what was limiting direct Cu-Cu bonding all agreed that copper bonding was not ready for prime time just yet. Yu a strong proponent of copper interconnect, noted that current copper bonding options have yield issues that have not yet been overcome “current requirements for pads are too large and the required CMP of the interfaces is causing dishing that must be handled...HVM of copper –copper bonding options is tougher than showing research samples”

When similarly asked about  hybrid metal/oxide bonding schemes where oxide / copper surfaces are polished flat, oxide bonded then subsequently oven annealed to strengthen oxide bond and form Cu-Cu bonds (as shown by Ziptronix and Leti) no panel members were willing to say that this technology was close to commercialization.  TSMC responded that these technologies required very flat surfaces which were difficult to obtain due to dishing and other issues and that in general such technologies were “not ready right now”.  ASE expanded that this option was not required to solve todays problems and therefore was being looked at as a interesting R and D solution which could find its niche later. During Q and A Cook of Ziptronix offered that she thought their technology was ready and simply awaiting the commitment of a significant player. When the panel questioned copper migration issues due to miss alignment of the Cu-Cu bonds, Cook offered that their process which encapsulates the copper pillars in nitride barrier. 

Rumors abound that TSMC is designing the apple A6 processor for ipad and iphone with 3D TSV. When asked to comment on this or whether Samsung was also offering TSV in their design of the A6 this question brought the expected “no comment” from TSMCs Yu and silence from the rest of the panel. Similarly no one would offer up comment about who would be supplying Sony who announced that they would require TSV interposers for their next Playstation upgrade.

When asked about timing for the expected HVM of wide IO memory stacks for tablets, Qualcomm responded probably 2013 and Hynix responded maybe 2015.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE................

IFTLE 93 2.5 / 3D at the 2012 IEEE ISSCC

There were several interesting 2.5 / 3D presentations at the recent IEEE ISSCC conference.

2.5D Integrated Voltage Regulator Using Magnetic Core Inductors on Silicon Interposer

Minimizing energy consumption is a performance goal of all of today’s devices including  microprocessors. Dynamic voltage and frequency scaling (DVFS) is a technique for performing “on-the-fly” energy-use optimization. Implementation of DVFS requires voltage regulators that can provide independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs).

Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, but the primary obstacle facing development of IVRs is integration of power inductors. This work by Columbia University and IBM presents “an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration” by  combining magnetic materials, chip-stacking design and a 2.5D chip packaging process. The power converters integrated onto the same chip, or into the same package, as microprocessors "significantly improves computational performance per watt of power consumed

They report that the technology can reduce power consumption, by 10-20% in a typical US data center

Inductors are fabricated on the silicon interposer in an elongated spiral with a Ni-Fe magnetic core encasing the copper windings on the long axis.  “The Ni-Fe is deposited under a magnetic biasing field so that the hard axis of magnetization forms along the width of the core as shown in the figure. Inverse coupling between adjacent inductors, is utilized to avoid magnetic saturation of the core.” The inductor fabrication involves successive electroplating deposition of the bottom magnetic core, copper windings, and top magnetic core. The windings are electrically isolated from the bottom magnetic core with a layer of silicon nitride, and from the top core with ”hard baked photoresist”.

(Click on any of the images below to enlarge them.)

IBM Stacked Memory on Processor

There have been rumors out there that IBM would be applying with their 3D technology in their upcoming Power7 devices. Their presentation at ISSCC may be the first look that we are getting at their early designs for processors stacked with cache memory using TSV technology.

This work describes a prototype 3D system, constructed by stacking a eDRAM memory layer and logic blocks from the IBM Power7TM processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology enhanced to include TSVs. The 3D stack is constructed using 50 µm pitch C4’s joining the front side of the thick processor chip to TSV connections on the back side of a thinned memory. The TSVs are Cu-filled vias that are ~20µm dia and <100 µm deep.

Standard design methodologies with some 3D extensions were used to design each stratum. TSV locations for power and clock were pre-defined to match a regular grid. Some sites were de-populated to accommodate the eDRAM blocks.

Tezzaron Technology Used for 2 Processors

Old friend Bob Patti at Tezzaron was involved helping fabricate two of the processor modules shown at this years ISSCC

Georgia Techs  3D-MAPS: 3D massively parallel processor with stacked memory

3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5 x 5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density

Tezzaron 3D technology was used to stack two logic dies using face-to-face (F2F) bonding, where the top die is thinned to 12µm and the bottom die is 765µm thick.  These F2F pads are used for signal and P/G connections between the two dies. The diameter of a F2F bonding pad is 3.4µm, and their pitch is 5µm. 3D-MAPS uses 235 I/O cells that are placed along the periphery of the core die. Each I/O cell contains 204 redundant TSVs, where each TSV connects between a metal 1 landing pad and a backside metal landing pad deposited on the backside of the silicon substrate. Each backside metal landing pad (56 x 56µm2) is wire bonded to the packaging substrate. The diameter, height, and pitch of a TSV are 1.2µm, 6µm, and 5µm, respectively

University of Michigan Centip3De

David Fick of the University of Michigan showed Centip3De another processor fabbed by Tezzaron. A 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM operating at near threshold voltage. The module has an un-thinned cache layer and a thinned core layer with WB connecting to TSV on the backside.

Hynix Dealing with Process Variation in a 3D Memory Stack

In general, commercial DRAM shows large process variation from chip to chip, which causes address access time variation (tAC).  In order to reduce the tAC variation, most high speed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption.   
Hynix in their paper entitled “A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface explains that this can be an even larger problem for stacked memory die. “For TSV-based stacked dies, large tAC variation results in higher power consumption due to short circuit current from data conflicts among shared IOs”. Since the number of IO  might be 512 or more for wide IO DRAM,  the additional power consumption can be very high. While it is desirable in mobile DRAM to exclude the DLL because of the power cost , TSV stacked DRAM for high-speed operation partially adopts a DLL in the master die (driver circuitry) . The DLL-based data self-aligner (DBDA) described by Hynix  reportedly reduces the data conflict time among stacked dies, consuming 283.2µW during read operation at 800Mb/s/pin. It dissipates 4.98µW in self-refresh mode with the help of leakage-current-reduction controller.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE..............

IFTLE 92 Advanced IC Packaging at InterNepcon Japan, Loss of a Dear Friend

At the recent InterNepcon Japan Exposition held at the Tokyo "big site" their "IC Packaging Technology Expo" contained some new information and some retreads that we have seen on IFTLE previously. Below I'll cover a few new items that may be of interest to you.

TI's Mark Gerber, a key player in bringing up their Cu pillar technology at Amkor addressed 3D packaging technology for next generation devices. Mark broke out current FC interconnect technologies into the following 4 categories indicating that fine pitch gold stud bumping was confined mainly to Japan.

(Click on any of the images below to enlarge them)



Sung-Il Cho of Samsung's test and package center looked at Samsung's Packaging Roadmap. He offered the following categorization for their DRAM, Flash and system LSI chips...



...and the following roadmap for flash technology development for solid state drives. Consistent with their corporate policy of holding new technology information "close to the vest" their inputs on 3D packaging with TSV were either ITRS roadmap slides or Yole roadmaps that have been published on these IFTLE pages before.



Keiichirou Kata of Renesas Advanced Package Development Dept. addresses their packaging roadmaps. He sees the major developing areas as FC BGAs, WLP and what he calls 3D Jisso (3D IC integration). Their FC technology roadmap is driven by desire for tighter pitches.



28 nm node chips will see a move to 108 um pitch and copper pillar bumps by the end of 2012.



Their proposed fan out WLP is an RDL first technology which they contend eliminates the issues of chip movement due to mold compound shrinkage.




They are moving to wide IO DRAM standards for low power DDR3 and beyond.



Ryoji Matsushima from Toshiba's Memory Packaging Engineering Dept. discussed equipment materials and processing issues for thin memory packages. High memory capacity, high memory access speed and thinner packages all point towards memory stacking with TSV.



Technical issues with thin packages are shown on the slide below.



In Memorium: Jackki Morris Joyner



This past week I was attending the IMAPS Device Packaging Conference in Ft McDowell AZ (coverage coming in a few weeks). Those of you who are long time readers of IFTLE know I am there every year and strongly support this IMAPS conference. In the end, what separates societies is people not content. Part of what makes IMAPS great to work with has been Jackki Morris, or as we knew her post marriage Jackie Morris Joyner. When she first told us of the impending marriage and that she was becoming Jackki Joyner we all teased her asking her to run around the buildng for us ( for our non US friends this is the name of a famous US Olympic runner) and she laughed along with us. Jackki was the kind of person who made your life better for having talked to her on the phone or corresponded by email. Everyone asks "how's it going" but she meant it. She genuinely cared about people... you just could tell.

The last time I talked with Jackki she was working the IMAPS table with her husband Cliff Monday night. When she saw me she gave me a hug and she turned on her computer and showed me pictures I had sent her of my grandaughters a few years ago. She had pages and pages of pictures of all the friends she had made through IMAPS because she just was that way. We shared funny stories of past conferences and laughed before I let her get back to work.

The next morning she was noticeably missing and Exec Dir Michael O'Donoghue revealed to several of us that Jackki had become quite ill during the night. By the time she made the hospital her heart had stopped several times and she was in intensive care with Cliff by her side. This cast a pall over the rest of the meeting and she remained in intensive are as we all left the meeting to go home. By the time I arrived home Friday she had passed away. The world is truly worse off today because this caring, loving person is gone.

Our prayers are with Cliff and her family

Anybody here seen my old friend Jackki
Can you tell me where she's gone
She cared and shared with a lot of people
But it seems the good they die young
I just turned around and she's gone

IFTLE 91 IEEE 3DIC Japan 2012 part 2

Continuing to examine presentations from the 3rd Int IEEE 3DIC Conf held in Japan in Feb 2012.

Copper Protrusion

In the last several years PFTLE and IFTLE have brought copper protrusion to the forefront as an issue [see "Researchers Strive for Copper TSV Reliability" Semi Int, 12/03/2009] and reported on technical solutions as they appeared from IMEC [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC..."]; TSMC [see IFTLE 34, "3DIC at the 2010 IEDM"] and others. IME has now reported on their study of 5 um x 50 um Cu TSV as they were annealed from 250 to 450C.

Cu expands vertically because it is constrained by the surrounding silicon substrate. Because it expands plastically it does not return to its original length when the sample is cooled down.

(Click on any of the images below to view the full-size version)



The effects of anneal temp, anneal time, via diameter and via depth are shown below where "room temp" refers to the protrusion present after anneal and return to room temperature and high temp refers to protrusion after anneal while still at the elevated temperature. As with previous studies they found that CMP after anneal retards any further protrusion if the temperature is again elevated.



Bottom line is that protrusion is minimized by small diameter, low aspect ratio TSV.

Samsung System LSI Division has also looked at the Cu protrusion issue and report similar results i.e that Cu protrusion can be reduced by heat treatment before CMP and that Cu protrusion and delamination strongly depend on TSV dimensions.

When the via diameter was in zone A all the vias showed high Cu extrusion and via delamination, but TSV diameters from zone B showed no problems.


Micro-cracking caused by Lateral Extrusion

Conference Chair Koyanagi and co-workers at Tohoku Univ also examined TSV dimensions and the effect of high temp annealing. An array of Cu TSV with diameters ranging from 3 to 30 um at three different pitches were annealed from 200 to 400C. Both the lateral and vertical protrusion of the copper was monitored.

Again larger diameter TSV (at a constant depth) show higher extrusion, but also that lateral extrusion (extrusion in the x-y after Cu has protruded from the surface) increased with anneal temp. For example 5 um TSV on a 10 um pitch extrude laterally 2 um at 400C. This would put them within 1 um of touching! Stresses induced by the TSV also result in microcracking "...on the periphery of the TSV array and in between the TSV." Careful choice of TSV size and pitch is recommended.



Cu-Cu Direct Bonding

Copper-copper direct bonding continues to be a popular topic due to the promise of fine pitch, low resistance interconnect which are more mechanically reliable than IMC bonding (Cu-Sn-Cu) and should show less electromigration issues. Such processes are currently limited by the required bonding time / temperature which are usually reported as 30 min / 350-400C. The holy grail appears to be a thin die Cu-Cu thermo compression bonding process which requires low bonding temp and pressure.

IMEC and TSMC have studied the direct Cu-Cu bonding of 5 x 40 um TSV with (3) different configurations ; (1) no nail head exposed (Cu CMP'd flat with the oxide surface; (2) flat nail head (cu CMP'd flat and then oxide recessed and (3) natural nail head (stop grind short of the nail head, pull back oxide revealing "dome" shaped copper protrusion. The matching landing pad is a Cu surface CMP'd flat with the oxide surface. After bonding they observed that the "no nail head exposed" and the "flat nail head" sample s delaminated even when the bonding temp and or the pressure was increased. They assumed failure was due to the low % area that is actually used to bond (less than 1%). So, what is good for the design (less than 1% of the area occupied by TSV) is not good for the strength of bonding. The dome bonding was better due to its ability to deform. IFTLE interprets this as an ability of the domed structured to deform allowing shorter TSV to now touch their pads and bond. IFTLE also thinks this is a good reason to look at hybrid bonding schemes such as proposed by Ziptronix [see PFTLE 48, "Opening the Kimono, Ziptronix gives details on DBI Process"] and CEA Leti [see PFTLE 103, "Show me the Copper"]

Stacking of Ultrathin Die

Standard 3DIC thickness has focused around 50 um for the last few years. IMEC has now shared their results of ultrathin (25 um) die stacking.

After temporary bonding and grinding, oxide is pulled back for Cu TSV reveal. The revealed "nail heads" are passivated with 3 um BCB and reconfigured with Cu/BCB RDL. Cu/Sn bumps are then fabricated on the landing pads. The 25um thick die are diced while still bonded to the carrier. They note that "this is required to have enough mechanical support during stacking"

Both NUF and WUF were looked at for underfill solutions. NUF is unfilled polymer dispensed onto the landing die prior to bonding and WUF is filled underfill film laminated to the thinned wafer while still on the carrier.



Issues with NUF were: (1) underfill trapped between the bumps;(2) voids between top and bottom die and (3) induced topography due to underfill shrinkage on cure. Shrinkage of the underfill upon curing and the CTE difference between a microbump and the underfill cause a bending of the die over the ubump connection. For an unfilled underfill and a 25um thick die a 40% increase in the drain current was observed to occur.

After several failed tries, they decided to focus on WUF with 60% filler loading. WUF was vacuum laminated onto the die and gave much better topography and the use of a filled underfill resulted in reduced stress.

They also found that increase in the die thickness from 25 to 50 um resulted in a stress reduction of 3X. Final conclusions were that 50 um thickness die were currently much better option for scalable manufacturable process and that reduction in the TSV diameter from 5 to 3 um will reduce the required KOZ by 64%.

Wireless Product with Design Partitioning

ST Micro and CEA Leti described their program to partition the digital and analog functions of a HD video transmitter onto separate die and stack them using Cu TSV and ubumps.



TSV are 10 um with a 40 um pitch and wafers are 80 um thick. Cu pillar interconnect are 25 um dia and 30 um high. Reliability tests were done at package level using JEDEC level 3. No delamination and no electrical failures were obtained after 1000 cycles.

--------------The next IEEE 3DIC Conference will be held in the fall of 2013 in San Francisco--------------

Coming up in IFTLE :
-advanced packaging from InterNepcon Japan
-3D as the ISSCC
-detailed coverage on the IMAPS Device Packaging Conference and more

For all the latest in 3D IC and advanced packaging stay linked to IFTLE............................