Finishing up on the IEEE
3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining
key papers from the conference.
Tohoku Univ - Lattice Distortions in Thinned Silicon
It is accepted that to achieve
compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However,
the ultra-thin nature of Si substrate leads to several problems such as weak
mechanical strength, warping and local deformation in the stacked die . Moreover, the weak mechanical strength of the
extremely thin die/wafer itself has a potential concern lead to die breaking
for 3DIC integration, because thin LSI chip with high density TSVs is highly
fragile and more easily damaged. Hence, it is important to understand the
impact of chip’s mechanical strength on device reliabilities decreasing die
thickness, especially below 50μm thickness.
Koyonagi and co-workers have
found that the Young`s modulus (E) of Si substrate begins to noticeably
decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of
the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted
which induces the Young`s modulus reduction and consequently weakens the mechanical
strength.
DRAM chip of 200μm thickness were bonded to a
Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured
retention characteristics of DRAM cell on these thicknesses of silicon are
degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM
cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm
thick chip.
They assume that the band-gap
energy in the thin chip is affected by the distortion of the lattice structure,
hence effect on a minority carrier lifetime, consequently shortening the
retention time of DRAM cell.
Fujitsu – Influence of Wafer Thinning on Backside Damage
Fujitsu is
known for their ultrathin WOW process [ see K. Fujimoto, “ Development of Multistack
Process on Wafer-on-Wafer (WOW)”, Proceed. IEEE Electronic Component Tech
Conf, 2010.]
Ultra-thinning
to 10 microns or less of Si wafer is expected to realize small TSV with low aspect ratio and coupling capacitance. Subsurface
damage following wafer thinning from the back of 300 mm wafers using three
different types of thinning process was investigated by means of Raman
spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse
grinding generates significant rough subsurface ranged several micron and
damage layer including amorphous and plastic-deformed Si along grinding
topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed
after thinning at least removal of 50 microns. However, plastic-deformed
subsurface layer with a thickness of 100 to 200 nm are still remained which
leaves an inside elastic stress layer ranging up to about 10 microns in depth.
Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables
to remove residual damages such as structural defects and lattice strains after
1-5 microns thick polishing while vacancy-type defects only remain.
The authors acknowledge that further investigations are
necessary to find “hidden residual defects” and to understand the influence of
thinning on memory devices (see Tohoku discussions above)
ASE
/ Chiao Tung Univ – Low Temp Bonding
ASE and National Chiao Tung Univ have studied three types of bonding,
including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D
interconnects.
Cu-In bonding and Sn/In-Cu bonding can form intermetallic
compounds at the bonding temperature lower than 180 C. Cu
and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa,
followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples
were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding
temperature of 180 C for 50 min
Cu/Ti samples were bonded face to face with a bonding
pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min. They add that Cu can be protected from
oxidation by capping Ti on Cu surface before bonding. This last structure is
especially significant if one can really do such bonding at 180 C . Their EDX
investigation of the interface shows that “…apparently there is a Cu layer at
the bonding interface instead of Ti layers…due to lower activation energy at
the surface, Cu tends to diffuse towards the surface …”
IFTLE feels this combination certainly deserves further study.
All bonded structures have shown excellent electrical
performance and reliability characteristics. Based on bond results, these
structures can be applied for low temperature bonding in 3D interconnects.
RTI
– 10um Pitch Bonding of Hetero Materials
Matt Lueck of RTI Int described their successful
demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch
interconnection of heterogeneous semiconductor die. InP die have been bonded to
Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps
on 10 μm pitch.
A key technological challenge facing the 3D integration
of heterogeneous semiconductors is the formation of high density metal
interconnects between dissimilar substrates, such as compound semiconductors
(CS) and Si. Due to the difference in the coefficients of thermal expansion
(CTE), one can expect: 1) some misalignment between microbumps fabricated on
the CS substrate and the Si substrate during bonding at an elevated
temperature; and 2) bond interconnects will experience shear strain as the
bonded die pair is cooled to room temperature and during any subsequent thermal
excursions.
To estimate the magnitude of the misalignment, they
calculated the relative change in distance between corner microbumps in a 10 μm
pitch 640 × 512 array on CS die vs. Si die. Operability was determined by
electrical testing of long daisy-chains of bumps.
The average channel yield was approximately 97% for both InP-Si
and Si-Si die pairs translating into the array operability greater than 99.99%.
The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal
cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous
Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8%
decrease in channel yield whereas those not underfilled showed a 13.9%
decrease.
They conclude that Cu/Sn micro bumps can be successfully
and reliably used for integration of InP and Si die.
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