IFTLE 148 The Future of Packaging: A Look From 50,000 Feet

There is a saying in American business that recommends if you really want to understand something you need to take a “50,000 foot look” (for those of you on the metric system, that’s 15.2 km). The logic behind this goes something like: if you're engaged in a battle and need to know how to position your troops, better to be looking down from above than be in the midst of the battle.  Exactly where the number 50,000 comes from, I haven’t a clue. 50,000 feet is way above the clouds and certainly would not allow you to see troop movements. If I had made up the phrase, I would have said, “Let's take a hot air balloon look” above the fray, but close enough to the ground to see what is going on.

Anyway, the IMAPS Device Packaging Proceedings have still not arrived (since March!), ditto on the April ICEP proceedings, and the ECTC is yet a week away. So, I thought we might  take  “a hot air balloon look” at our industry.

The front end drives everything

Even though you came to this blog to read about packaging, clearly understand that packaging is driven by IC fabrication (the front-end) and that will never change.

IC fabricators make their big profits on the leading edge node, not on the older, more available nodes.

New materials are introduced on the leading edge, and once these processes are locked down (qualified), they are very hard to change.  This is why equipment suppliers and materials vendors have always spent much of their hard-earned profits on trying to get qualified into the next generation node products.

The End is Coming! Soon. Maybe.

Everyone reading this blog understands the “Moore's Law Coming to an End” arguments. Exactly when it will happen is, to me, less relevant than the fact that it is happening or has already happened for many mid-tier IC fabricators.

Some top-tier fabs / foundries will find a way to move forward past 22nm to 14nm and beyond, but the important point is that the vast majority won’t. This is not because the technology won’t be available to them, but rather because it will be too expensive. You have seen my slides on this before. Since it is very important that you understand it, I will show them to you again.

The conclusions are simple:

1. There are only a few companies with enough revenue to justify developing and building $6B+ fabs for 22nm and beyond.

2. There are very few products that have enough volume to absorb the design costs inherent to 22nm and beyond designs.



The players that can afford to move forward at this point appear to be Intel, Samsung, TSMC, GlobalFoundries, UMC and Hynix. Maybe one or two more appear through consolidation, but, in general, that’s it.  

Packaging Is Becoming More and More Important…and valuable

In the future, product differentiation in most product lines will be achieved by the packaging used, not by the incorporation of chips of the latest node.  What we are seeing in the industry is TSMC, Samsung and maybe others making a strong move into IC packaging.

Equipment Vendors Consolidating as Customer Base Shrinks

For equipment vendors, the leading edge node customer base is shrinking, and thus you see some of them (litho, 450mm) requiring investments from the IC fabricators before putting money into future node developments.

Typical front-end equipment vendors led by Applied Materials, Lam etc. are also  acquiring  back-end equipment vendors to expand their product offerings.

Front-end equipment vendor acquisitions in back-end packaging equipment was, at first, met with skepticism by the packaging community, since front-end equipment has significantly higher margins than back-end packaging can afford. More recently, they have realized that the front-end chip fabricators are moving into the back-end packaging business and are going to their traditional equipment vendors to meet their needs.

Material Suppliers Consolidation Coming ?

It is only logical that the next round of consolidation will come from the materials suppliers.

Materials suppliers have traditionally been quite ignorant when it comes to the actual applications where their materials are to be used. Most blindly follow the roadmaps put out by the industry without really understanding them. In several instances, the low K fiasco of the late 1990s comes to mind. They followed the Pied Piper right over the cliff with many of them loosing tens of millions of dollars, trying to develop spin on polymer dielectrics that were really never going to be used.  



Materials suppliers, once again, need to be very careful when developing for the sub 22nm nodes (on chip or packaging) or for 450mm processes, because the number of companies working on these programs is likely to be significantly greater that the number of potential customers. History tells us that there will only be one or two processes / materials sets chosen by these six-ish players and the potential losses incurred here, by the materials suppliers whose solutions are not chosen, may in fact lead to the eventual consolidations that I predict.

In addition, speaking to many fabs and foundries they all appear to be attempting to minimize the number of suppliers they engage as a cost containment issue. I will not be surprised to see old qualified processes trying to replace generic materials with favored vendor equivalents.

These are not unusual outcomes; in fact, they are natural for an industry that is entering its “mature” stage, and that is certainly where we are headed.  

Hope to see many of you all in Vegas at ECTC.

For all the latest in 3DIC and advanced packaging, stay liked to IFTLE.



IFTLE 147 IME Updates 2.5D; Qualcomm Updates 2.5 / 3DIC at ICEP

IME Updates Interposer Research


In the latest issue of Future Fab Int Singapores IME updates their 2.5D through-silicon interposer (TSI) technology development [link]

GQ Lo, deputy Director Director of Research, and his 3D group point out that "3D IC...is confronting bottlenecks, such as tools for designing optimal 3D systems and thermal solutions for 3D ICs" and that "2.5D through-silicon interposer (TSI) technology is gaining momentum, both in the foundry and the outsourced semiconductor assembly and test (OSAT) universe."

They state that interposer technology provides easier fabrication, alleviates 3D thermal bottlenecks and supports the fabrication of heterogeneous integration. They demonstrate the fabrication and characterization of a 2.67 x 4.3 cm2 interposer on a 300 mm processing line. Processor + memory integration is an ideal 2.5D application since "dies can be heterogeneous (e.g., logic and memory) and can belong to different technology nodes (e.g., 28nm for logic and 40nm for memory, or 130 nm for BiCMOS chips."

The TSV (12 µm x 100 µm ) were Bosch etched into a 300mm wafer. TEOS oxide was deposited to isolate the TSV from the silicon substrate; Ti / Cu sputtered as a barrier metal and copper seed. Copper was electroplated, and overburden removed by CMP after copper anneal. Three single-damascene processes were applied to form frontside M1, via and M2 on top of the TSV.

ZoneBOND technology was used for wafer temporary bonding and de-bonding. TSV wafer was back-ground to near TSV depth, the remaining silicon substrate was etched to expose the TSV from the wafer backside and low temp dielectric films deposited and CMP’ed. Back side barrier metal and Cu seed were sputtered on the back side dielectric, and the RDL was plated up, patterned and bumped.

The cross-section of TSV and FS metal is shown below.

The electrical performance (C-V and I-V curves) of the interposer was characterized for TSV capacitance (CTSV) and leakage current after top M2 metallization and before TSV reveal.

The leakage between four TSVs with connection pad to silicon substrate (measured TSV good dies after C-V characterization) is less than 1 pA for a voltage range 0-100 V, suggesting satisfactory isolation between the TSV and the silicon substrate.

The yield of the front side M1-TSV-BS RDL chain and front side M2-via-M1-TSV-BS RDL chain were 90 percent and 85 percent, respectively.

Resistance of the TSV and backside RDL (line/space 10/10 µm) are shown below:

 

Qualcomm at ICEP

At the recent ICEP (Int Conf on Electronic Packaging) in Osaka Japan, Qualcomm’s Umi Ray presented "Architecture Trends in Mobile Industry and Impact on Packaging and Integration," updating their smartphone activities "one device many functions." They supported the Gartner projection that 5 billion smartphones will be sold between 2012 and 2016.



Ray proposed that we would be seeing 2.5 / 3D in our phones soon and showed the following roadmap, although the time axis was left vague:

The first implementation target will be wide IO memory on logic and so far, they have seen "no technical show stoppers." As we have discussed in the past, pricing remains the key challenge.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 146 TSMC Apple Rumors; Gartner OSAT Mkt Numbers; Novati

More Taiwan rumors on TSMC / Apple relationship

 Digitimes reports that TSMC will get  100% of the application processor orders for 2014 model iPhone [link]

 Digitimes further reports that  "in order to satisfy the huge demand from Apple, TSMC has begun equipment move-in for the phase-5 facility of its 12-inch fab …. Fab 14, Phase 5….[this] facility will be ready for production by the end of 2013, the sources indicated." TSMC has previously disclosed that the Fab 14, Phase 5 facility is a 20nm-capable fab, scheduled to begin volume production in early 2014.

They further report that Samsung, which produces APs for the existing iPhones, will still manufacture chips for the upcoming model scheduled to be released in the second half of 2013.

OSATS Market at $24.5B

Gartner estimates the worldwide outsourced semiconductor assembly and test services market totaled $24.5 billion in 2012.

As shown below ASE remains No. 1, with revenue of $4.4B with packaging accounting for about 80 percent of the company's total assembly/test/materials revenue.

Amkor revenue was $2.8 billion, and  SPIL third at $2.2 billion, with 90 percent of the revenue from packaging and 10 percent from test. STATS ChipPAC is fourth with $1.7B.

Powertech Technology (PTI) at $1.4B is differentiated from the others in that the majority of its revenue comes from servicing the memory segment of the semiconductor market.

As shown below Taiwan currently controls nearly 50 percent of this market, with he next largest players, USA, Japan and Singapore far behind at about 10 percent each.

The full Gartner report can be found here [link]

Novati

Bob Patti of Tezzaron, a 3D industry leader for more than a decade recently gave a presentation explaining their acquisition of what is now called Novati. Many of you may know that this was the former Sematech Austin fab which over the years morphed, was   merged with Cyprus Semiconductor emerging as SVTC and now has been sold to Tezzaron. This is shown in the slide below.



Below is a photo of the location and a list of current capabilities



Bob indicates that their TSV connection to BEOL wiring happens  "near end of line" (reminiscent of IBM),  as shown below:

Their plan is to be a foundry for 2.5D interposers as well as 3D stacking. IFTLE will be keeping an eye on their future activities.  

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.