IFTLE 145 GPU Roadmap, IEEE 3DIC back in SF; ConFab 2013 Pkging

NVIDIA has publically updated their roadmap with the announcement of the GPU family that will follow 2014’s Maxwell family. That new family is Volta which will use stacked DRAM, which will be connected to the GPU with TSV.

NVIDIA is targeting a 1TB/sec bandwidth rate for Volta, which to put things in perspective is over 3x what GeForce GTX Titan currently achieves with its 384bit, 6Gbps/pin memory bus (288GB/sec). This would imply that Volta is shooting for something along the lines of a 1024bit bus operating at 8Gbps/pin, or possibly an even larger 2048bit bus operating at 4Gbps/pin. Volta is still years off, but this at least gives us an idea of what NVIDIA needs to achieve to hit their 1TB/sec target [link]

GPU Technology Conference in San Jose. CEO Jen-Hsun Huang was visibly anxious to unveil the company’s Volta, their upcoming GPU targeted for a 2016 release.

"Volta is going to solve one of the biggest challenges facing GPUs today, which is access to memory bandwidth," Huang told the attendees.

Move up http://i.forbesimg.com t Move down The Volta GPU will introduce stacked DRAM which will deliver 1 terabyte per second of memory bandwidth.

Below is a shot of the Volta with stacked DRAM (drawn to scale)

Huang didn't provide a timeline for Volta's release, but 2016 seems reasonable since  Nvidia debuts new GPU architectures every two years.

Huang said that Nvidia will be putting the stacked DRAM and the GPUs onto the same silicon substrate and inside of the same packaging before it welds that package to a peripheral card.

4^th Annual IEEE 3DIC Coming to SF in October

The IEEE 3D meeting 3DIC has rotated through Germany and Japan and is back in San Francisco this October 2-4 (link). Paper submission deadline is April 30^th.

3D & Packaging Lineup for SST Confab

The full description of SSTs ConFab  2013 can be found here (link)

This years packaging and 3D sessions are co-sponsored by the Component, Packaging and Manufacturing Society (CPMT) of IEEE.



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IFTLE 144 Personnel Changes in Taiwan; Glass Usage in WLP

Apologies for the delay in covering the IMAPS device packaging conference this year. I normally get access to the manuscripts as I am leaving the show to insure timely coverage. This year that was not possible. IMAPS' move of their office to the RTP NC area is causing further delays (they will soon be my neighbors), so I await the conference CD like the rest of the attendees.

Personnel Changes in Taiwan

The word from Taiwan is that Doug Yu, who has been responsible for the R&D of exploratory technologies including FEOL, BEOL and 3D IC has been refocused on just packaging, especially their CoWoS 2.5D offering.  IFTLE thinks this move shows that TSMC is serious about expanding  this business within their company.

We also hear that Ho Ming Tong currently General Manager and Chief R&D Officer at ASE, who has been a strong supporter of 3DIC, and is actually credited with coining the phrase 2.5D,  is moving further up the corporate ladder at ASE.

Congrats to both gentlemen!

 The Current and Coming Use of Glass in WLP

 We have recently discussed Asahi Glass entering the 2.5D glass interposer market [see IFTLE 141, "100GB Wide IO memory; AGC GlassInterposers; Nvidia talks stacked memory"] and the general use of glass interposers for 2.5D fabrication [ see IFTLE 54 ,"2011 ECTC and GlassInterposers"

Yole Developpement’s Amandine Pizzagalli has just issued a report "Glass Substrates for Semiconductor manufacturing," where she has examined the potential applications for glass in wafer level packaging and reported on the current and projected market size. A sample of the report can be found here [link]. The functions that were examined include: carriers for thinning in 2.5/3D; capping layers for CMOS image sensors, wafer level optics, structural substrates and wafer level capping.

A grid of application vs function would look something like this.



The market breakdown by end application is shown below with MEMs and image sensing being responsible for over 50 percent of the market for more than the next five years..



Total market glass market is reported to be  $158M in 2012. Schott (Germany) , Tecnisco (Japan), PlanOptik (Germany), Bullen(USA) and Corning (USA) reportedly share 70 percent of the market, driven mainly by demand for WL capping [CIS application (see below)].

CS wafer level glass capping is shown below .





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IFTLE 143 HMC status; Pkging Materials $$ now Exceed Wafer Fab Materials

Hybrid Memory Cube Consortium

Twenty-five years after Ronald Regan made his famous demand in Berlin "Tear down this wall," Micron, Samsung and early hybrid memory cube consortium members promised to tear down the memory wall [ see IFTLE 38, "IFTLE 38 of Memory Cubes and IvyBridges - more 3D and TSV"], which was viewed as holding up the progress of future microelectronic products.

Since recent IFTLE reports have indicated that delays in 2.5/3D commercialization have been due to a lack of TSV memory stacks (or at least TSV memory stacks at the right cost point) [see IFTLE 140 "Important Apple Rumors; Xilinx not Deserting 2.5D;Book to Bill Improving"], we thought it was appropriate to take a look at the current status of HMC. Updates on their progress can be found here [link].

ARM, HP, and SK Hynix joined former members including Micron, Samsung, Altera, IBM, Microsoft, AMD, Fujitsu, ST Micro, Marvell and Xilinx in June 2012.

The Hybrid memory Cube [link]

 The group has recently issued version 1.0 of its specification for a vertical memory stack with a defined logic-layer interface. The group is reportedly changing focus to higher-speed variations of a DRAM stacked using TSV technology. They want to increase data rate across modules from the current 10 - 15 Gb/sec up to 28 Gb/sec.

Micron said it will deliver engineering samples of 2 and 4 Gb versions of the stack by this summer with commercial production scheduled for late 2013 or early 2014.

 High-speed networking vendors will probably be the first to commercialize with  HPC-centric applications next in line. Initial HMC implementations will be DRAM, but multi-memory stacks that employ NAND flash and DRAM are expected to follow.[link].

  
2012 Semiconductor Revenue

Gartner reports that total worldwide semiconductor revenue was $299.9B in 2012, down 2.6 percent. The top 25  vendors accounted for almost the same portion of the industry's total revenue as compared to 2011.

Intel retained its number one position despite a 3.1 percent revenue decline  (due to decline in PC shipments).  Number two Samsung saw weak DRAM growth although its overall revenue increased from smartphone ASICs and application-specific standard products. Qualcomm, which climbed to number three, continues to benefit from its leading position in wireless semiconductors. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place in semiconductor shipments.

2012 Top 10 Semiconductor Vendors

2012 Materials Market

Semi just reported that the global semiconductor materials market decreased 2 percent in 2012 to $47.11B the first decline in three years. Packaging materials exceeded wafer fabrication materials for the first time ever $23.74B vs $23.38B.

For the third year in a row, Taiwan is the largest consumer of semiconductor materials due to its large foundry and advanced packaging base. Materials markets in China and South Korea also experienced increases. The materials market in Japan contracted 7 percent, with markets also contracting in Europe and North America.

   2011-2012 Semiconductor Materials Market by World Region

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IFTLE 142 GlobalFoundries 2.5 / 3D at 20nm; Intel Haswell GT3; UMC / SCP Prototype Details

GlobalFoundries

 A year ago [see IFTLE 102, "3.5D Interposers tosomeday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predictsConsolidation"] GlobalFoundries (GF) CTO Bartlett announced the installation of TSV production tools for the company's 20nm technology platform and announced that "the first full flow silicon with TSVs was expected to start running at Fab 8 (Saratoga NY) in Q3 2012 with mass production expected in 2014 and the 2.5D line ( their 65 nm Fab 7 line in Singapore) had  a similar time schedule as the 3D line in the United States."

Last week, GlobalFoundries announced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in N.Y., the silicon foundry vendor manufactured TSV test wafers using their 20nm-LPM process technology, and at Fab 7 in Singapore, the company demonstrated a 65nm 32mm x 26mm interposer test vehicle for 2.5D chips. Both 2.5D and 3D are set for a 20nm introduction, full qualification by next year and non-early adopter production in 2015.

They are using a 6 x 60 um vias middle, copper TSV  as shown in the figure below. Interposer size is limited by reticle size i.e. 25-30 mm.

Dave McCann, VP of packaging technology at GlobalFoundries, reports that GF is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. "2.5D is already here," he added. Several 2.5D test structures were shown that were collaborations with Amkor.

While foundries TSMC and Samsung [see IFTLE 133, "SEMI ISS 2013 Comments from Samsung, GF,Intel and others"] are both offering turnkey solutions,  GlobalFoundries and UMC are supporting a partnering ecosystem where they will handle the traditional front-end steps and the "via creation" process and then will hand off the traditional backend steps such as temporary bonding/debonding, grinding, assembly and test to traditional packaging houses such as ASE, Amkor SCP and SPIL.

A year ago, GF announced hopes of shipping 28 and 20nm 3D chip stacks in 2014. Now, GF states only the 20nm chips will be used in stacks and they may not ship in volume till 2015.

Intel Haswell GT3

This past fall [see IFTLE 123: Intel's Bohr on3DIC] IFTLE reported rumors that Intel would be using TSV stacked DDR4 memory in their Haswell-EX platform for enterprise computing.

Haswell is the codename for the successor to Ivy Bridge architecture. Intel is expected to release 22nm CPUs based on Haswell around June 2013 according to leaked roadmaps. Current rumors have it that the Haswell GT3 will be the introduction point for 2.5D stacking and interposers. Semiaccurate [link] reports that Intel codename "Crystalwell" is not L4 cache on package but rather is GPU memory on an interposer. They indicate that the GT3 variants of Haswell will have 64MB of on-package memory connected through an ultra-wide bus.

Reports were that Haswell needed lower memory power consumption, higher memory bandwidth, and memory capacity that DDR3 could not provide but wide IO TSV based memory stacks could. Based on recent reports from the Semi 3D summit where ST Ericsson’s Kimmich concluded that "although 3D TSV technology appears ready for mass production, wide IO technology is not yet a fit for mainstream smartphones. LPDDR3 and LPDDR4 will be used in this application due to better thermal performance and lower cost."  [see IFTLE 134 “SEMI 3D European Summit – Isthe Wide IO Driver Dead ?”]                                                                        

IFTLE must ask whether these Haswell "requirements" can be met with the newly described LPDDR3 and LPDDR4 solutions, which do not use TSV technology.

UMC / STATS  Update

A few months ago, IFTLE reported that foundry UMC and OSAT partner STATSChipPAC (SCP) had announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip below).  This was developed under their open ecosystem collaboration using UMC’s foundry capability and STATS ChipPAC’s packaging capabilities. [See IFTLE 135, "UMC / SCP Memory on Logic"]

Several readers have reported that this structure (above) is from a TI OMAP 5 platform application processor and that the program with UMC and SCP was terminated when TI dropped out of the application processor market. (Thats probably why the xsect image was made available!)

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