IFTLE 89 Advances in CMOS Image Sensing

It was 5 years ago in the the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS) [see "PFTLE 12 Imaging Chips with TSV announced..."; PFTLE 16, "More TSV Commercial capacity on line"; PFTLE 24, "ST Micro announces more CMOS Image Sensor Packaging Capacity with TSV"; PFTLE 57 "Toshiba CIS Camera Module Details..."; etc]. The next step of circuit repartitioning and stacking was interrupted by "back side imaging" [BSI], which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel, which is really important as the pixels are getting smaller and smaller. [see PFTLE 40, "Backside Illumination next for Next Generation CMOS Image Sensors"; PFTLE 46, "on Mechanical Bulls, Rollercoasters and CIS with TSV."

For those of you needing a refresher about how this is done, below is a process flow that Yole Developpment released in 2010 starting with SOI wafers.

(Click on any of the images to enlarge them)

From SOI to Bulk Silicon

Last spring Chipworks announced that Sony had moved from an SOI based process to a bulk silicon process. [link] It is unclear yet whether this will become an industry wide trend.

Chipworks found that while previous Sony BSI sensors they had analysed were fabricated using an SOI starting wafer, with the 1.1µm BSI generation, Sony migrated to using bulk silicon substrates instead of SOI. Chipworks commented that SOI is a more costly substrate, but likely an easier process to implement. They presume that Sony was able to identify the yield limiting contributions from the bulk polishing process, and fine tune the yield to achieve a high yielding and very cost effective process. This process would require a SiO₂ bonding process.

In late August Ziptronix announced that Sony had taken a license on Ziptronix's patents regarding oxide bonding technology for backside illumination imaging sensors [see IFTLE 65, "...Ziptronix Licensing News"]

With BSI fully implemented, it appears that practitioners have now turned their sites back to repartitioning the circuitry and creating true stacked 3D IS structures.

Sony reveals stacking in BSI CMOS Image Sensor

In January Sony announced that it had developed "the next generation back-illuminated CMOS image sensors" by separating the pixel section containing the back-illuminated structure pixels from chips containing the circuit section for signal processing, which is in place of supporting substrates for conventional back-illuminated CMOS image sensors. [link] This results in:
-More compact image sensor chip size
-Higher image quality of the pixel section by optimizing the manufacturing processes for superior image quality on the pixel layer
-Faster speeds and lower power consumption by adopting the leading edge processes for the circuit section

By this stacked structure, large-scale circuits can now be mounted keeping small chip size. Furthermore, as the pixel section and circuit section are formed as independent chips, a manufacturing process can be adopted, enabling the pixel section to be specialized for higher image quality while the circuit section can be specialized for higher functionality, thus simultaneously achieving higher image quality, superior functionality and a more compact size. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits. Basically some of the attributes that we have been ranting about for 3DIC for the past 5 years. Samples will be shipped starting in March, 2012.

Poly SI TSV found in the Toshiba BSI CIS from Fujifilm Camera

Chipworks reverse engineering analysis of the Toshiba HEW4 BSI TCM5103PL 16 Mp, 1.4um Pixel Pitch CIS found inside Fujufilm F550 EXR camera. The CIS was fabricated using the Toshiba Oita 300 mm wafer line, using a 65 nm logic process adapted to BSI image sensor production. Fellow SST blogger Dick James [link] was kind enough to share more of the details for our IFTLE readers.

With BSI, the I/O pads end up on the bottom side of the sensor silicon (which is bonded to a handle wafer so the pads are burried). To get to the pads, you need some means of creating a via through the silicon to the front side metal. Very high density arrays of polysilicon filled through silicon vias (TSVs), to form the electrical interconnect between the back side aluminum bond pads and the front side copper lines on the CMOS integrated circuits. These are the first true submicron TSVs that Chipworks has seen deployed in volume production.

Chipworks notes that: "...closely packed, poly-filled submicron TSV... technology is non-trivial to implement. Once mastered and with appropriate economies of scale in play, however, this advanced TSV process saves valuable silicon area and can reduce the size of the camera module."

Applied Materials Targets BSI Sensors Manufacturing

Applied Materials recently announced the Applied Producer Optiva CVD system aimed at the manufacture of BSI sensors. "Emerging BSI image sensor designs present a new opportunity for Applied Materials to provide customers with the technology they need to be successful in this rapidly growing market"

The Optiva low temperature process runs on their Producer platform, capable of depositing low temperature, conformal films that boost the low-light performance of the sensor while improving its durability. The system enhances the performance of the microlens by covering it with a tough, thin, transparent film layer that reduces reflections and scratches, and protects it from the environment. Importantly, the Optiva tool is the first CVD system to enable 95% conformal deposition at temperatures less than 200C. As typical bonding adhesives have thermal budgets of approximately 200C, all subsequent processing on these temporarily bonded wafers must be done below 200C.


iSuppli estimates that 75% of all smartphones will be fitted with BSI sensors in 2014, up from just 14% in 2010. 2014 demand is estimated at 300 million units.

Coming up in IFTLE:
- Advanced packaging highlights from NEPCON Japan
- 3D highlights from the IEEE 3DIC Conference in Japan

For all the latest in 3D IC integration and advanced packaging stay linked to IFTLE........

Hope to see you all at the IMAPS Device Packaging Conference in Arizona next month!
IFTLE will be hosting a session on 2.5/3D Infrastructure development.