In late June Elpida announced what it claims is the thinnest available DRAM device, a new 0.8 mm four-layer package of 2GB DDR2 mobile RAM chips, assembled using package-on-package (PoP) technology. [link]
Customers have been using two-layer 0.8mm packages, rather than the thicker 1.0mm four-layer PoP, so systems needing 8GB of DRAM needed two stacks of 4GB product. Now they can get four layers of 2GB in one package. Yields and cost are reportedly the same as for existing 1.0mm products. Advantages of PoP for mobile devices includes: mounting space is reduced, individual packages can be tested, less wire bonding used (minimizes losses. Volume production ramp is slated for 3Q11.
3D IC Memory Stacks with TSV Now Shipping
A few days later Elpida, who exactly a year ago made headlines as the first to announce commercialization of memory stacked with TSV, [ see IFTLE 8, “3D Infrastructure Announcements and Rumors”] has now announced that it had begun sample shipments of DDR3 SDRAM (x32-bit I/O configuration) made using TSV stacking technology.[link]
The device is a “low power 8-Gb DDR3 SDRAM that consists of four 2-Gb DDR3 SDRAMs fitted to a single interface chip using TSV”. Target applications reportedly include tablet PCs, extremely thin PCs and other mobile computing systems. The new TSV DRAM will reportedly enable significant energy savings as well as making portable electronic devices smaller, thinner and lighter. Elpida believes that the new devices in notebook PCs will demonstrate a 20% reduction in operating power and a 50% reduction in standby power compared with systems that use the standard SO-DIMM configuration which use standard wire bonding technology. Power consumption is reduced because the TVSs shorten the interconnect between the chips, thus reducing parasitic resistance and capacitance. In addition, chip height is decreased and the DIMM socket is eliminated. Chip mounting area is reportedly reduced 70%.
This latest Elpida announcement serves to back up the statement that global 3D roadmaps appear to be converging on 2012 as the breakout year for TSV based memory stacking. [see “3D roadmaps Begin to Converge”]
MOSIS ready for 3D IC prototyping
In mid June MOSIS announced their Multi Project Wafer (MPW) services would now allow users to test out 3D-IC concepts using the same provider and model they currently use for their standard semiconductor processing. MOSIS has previously been known for its low-cost prototyping and small-volume production service for VLSI circuit development [www.mosis.com].
Working with Tezzaron and Mentor Graphics, MOSIS will manage MPW projects including reticle creation, fab reservations, final packaging and testing, and other logistics.
The Tezzaron process will enable designs using tens of millions of TSVs with dimensions as small as 1.2 x 6 um and 2.4 um pitch, producing up to 300,000 vertical interconnects per mm sq. Tezzaron will also provide backend manufacturing steps including wafer thinning, backside metal and wafer bonding.
Mentor Graphics provides DRC and LVS tools that support 3D-IC physical verification, ensuring that designs are correct and will meet 3D process requirements and are manufacturable.
Customers can use the MOSIS 3D-IC service to create proof-of-concept ICs that demonstrate the use of high-density TSVs in various applications.
TSV Going Where the Sun Don’t Shine
Medigus, a leading developer of endoscopic and visualization medical devices, and TowerJazz, announced successful sampling of the second generation of TowerJazz's CMOS imager that serves in Medigus' line of disposable miniature cameras. The use of disposable cameras eliminates the need for the very expensive and time consuming sterilization process commonly associated with endoscopic procedures. The camera’s diameter is only 0.99 mm, the first video camera in the world with a diameter smaller than 1 mm. Medigus will begin supplying samples of the camera to customers in Japan and in the US for cardiology procedures. The camera will be integrated in Medigus’ other endoscopy products.
The disposable camera sensor will be manufactured in TowerJazz’s Fab 2 using its 0.18-micron CMOS image sensor process and will be integrated into the camera produced in Medigus' manufacturing facilities. TSV are used to minimize the camera’s size and reduces production costs in high volumes.
For all the latest in 3D IC and Advanced Packaging stay linked to IFTLE…..
No comments:
Post a Comment