IFTLE 48 SEMATECH Addresses the Reliability Impact of Stress on 3DIC

The latest SEMATECH workshop “Design for Reliability Workshop – Stress Management for 3D ICs Using Through Silicon Vias”, in collaboration with Fraunhofer IZFP, and chaired by SEMATECHS Larry Smith, was held in March in Santa Clara. The keynote by Prof Paul Ho, U Texas,“Reliability Challenges for 3D Interconnects” served as a tutorial that outlined some of the basic incremental reliability challenges associated with the 3D technology. A presentation “Cu TSV Reliability: Modeling, Test Structures and Measurement Techniques” given by Victor Moroz of Synopsys, summarized some of the experimental work done at IMEC and presented data relating the electrical effects and stress in specific 3D structures. A paper “Thermo-Mechanical Reliability of TSV Packages”, presented by Xi Liu and Suresh Sitaraman of Georgia Tech provided an overview of the 3D state of the art work at package level. Three presentations “Design For Reliability of BEoL and 3-D TSV Structures—A Joint Effort of FEA and Innovative Experimental Techniques” presented by Juergen Auersperg of Fraunhofer, “Role of Thermo-Mechanical Modeling in 3D TSV Reliability Evaluations” by Kamal Karimanal of GLOBALFOUNDRIES, and “3D IC Reliability: A New Frontier” by Raymond Wang of ASE, demonstrated the use of various FEA approaches for modeling 3D structures. The workshop goals was to examine the mechanical stress-driven failure mechanisms, associated test vehicles, and characterization and modeling methodologies which pertain to the via- middle through-silicon-via (TSV) 3D stacking technologies.

Before I take a look at some of what was presented,  I’ll reiterate that I think readers of this blog come here for 3DIC and advanced packaging insight and part of that insight is knowing the latest spots to retrieve useful information.

We have previously discussed the SEMI/ SEMATECH alliance that is in place [ see IFTLE 33 “Micron 3D Response, SEMATECH Stds, Leti 300 mmLine” ] Semi has also been developing a Wiki site where important areas in microelectronics are to be discussed [link ] From this page you can access the 3DIC tab which leads to discussions about 3DIC. In addition SEMI /SEMATECH has now started a page [link] which covers “3D Interconnect Wiki: Stress Management for TSVs”. If you get nothing else from this blog, go to these two sites and acquaint yourself with what’s available.

Paul Ho – U Texas

Ho has examined the effect of TSV scaling on keep out zone (KOZ) and concluded that the near surface stresses degrade the carrier mobility and thus define the KOZ through the piezoresistivity effect. Defining KOZ as no more than 10% decrease in mobility :

• KOZ scales with the square of TSV diameter.

• KOZ minimized at a TSV aspect ratio less than 3
• KOZ is larger for analog devices than digital devices.

• The KOZ can be significantly reduced by using annular TSV.

Victor Moroz – Synopsys / IMEC

Synopsys / IMEC made a presentation on the characterization and modeling of 3D IC with via-middle TSV. Their studies on copper fill chemistries showed that chemistry “C” had 3X the stress of two other comparable materials. This copper had a finer grain structure and showed little to no grain growth after temp cycling.

They found no significant change in TSV C-V behavior before and after thermal cycling. When measuring the minority carrier lifetime from he transient response of a MOS capacitor they saw no significant change in TSV C-V behavior before and after thermal cycling.

After proper thermal treatment to minimize “copper pumping” (copper protrusion) they found no damage to M1 or M2 above the TSV . Examining the impact of TSV generated stress on the transistor performance they found good agreement between modeling and obtained data.

When examining the impact of Cu/Sn microbumps on N-FET logic devices of dies thinned to 25 um , they found a 40% impact on NMOS current due to he underfill that was being used to reinforce the interconnect bumps. Without underfill, no impact on current was observed. The zero stress temp was found to be ~ 160 C , i.e the curing tem of the underfill (as expected). The explanation is that the shrinking underfill bends the thin die around the Cu/Sn bump generating the observed stress.

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