IFTLE 48 SEMATECH Addresses the Reliability Impact of Stress on 3DIC

The latest SEMATECH workshop “Design for Reliability Workshop – Stress Management for 3D ICs Using Through Silicon Vias”, in collaboration with Fraunhofer IZFP, and chaired by SEMATECHS Larry Smith, was held in March in Santa Clara. The keynote by Prof Paul Ho, U Texas,“Reliability Challenges for 3D Interconnects” served as a tutorial that outlined some of the basic incremental reliability challenges associated with the 3D technology. A presentation “Cu TSV Reliability: Modeling, Test Structures and Measurement Techniques” given by Victor Moroz of Synopsys, summarized some of the experimental work done at IMEC and presented data relating the electrical effects and stress in specific 3D structures. A paper “Thermo-Mechanical Reliability of TSV Packages”, presented by Xi Liu and Suresh Sitaraman of Georgia Tech provided an overview of the 3D state of the art work at package level. Three presentations “Design For Reliability of BEoL and 3-D TSV Structures—A Joint Effort of FEA and Innovative Experimental Techniques” presented by Juergen Auersperg of Fraunhofer, “Role of Thermo-Mechanical Modeling in 3D TSV Reliability Evaluations” by Kamal Karimanal of GLOBALFOUNDRIES, and “3D IC Reliability: A New Frontier” by Raymond Wang of ASE, demonstrated the use of various FEA approaches for modeling 3D structures. The workshop goals was to examine the mechanical stress-driven failure mechanisms, associated test vehicles, and characterization and modeling methodologies which pertain to the via- middle through-silicon-via (TSV) 3D stacking technologies.

Before I take a look at some of what was presented,  I’ll reiterate that I think readers of this blog come here for 3DIC and advanced packaging insight and part of that insight is knowing the latest spots to retrieve useful information.

We have previously discussed the SEMI/ SEMATECH alliance that is in place [ see IFTLE 33 “Micron 3D Response, SEMATECH Stds, Leti 300 mmLine” ] Semi has also been developing a Wiki site where important areas in microelectronics are to be discussed [link ] From this page you can access the 3DIC tab which leads to discussions about 3DIC. In addition SEMI /SEMATECH has now started a page [link] which covers “3D Interconnect Wiki: Stress Management for TSVs”. If you get nothing else from this blog, go to these two sites and acquaint yourself with what’s available.

Paul Ho – U Texas

Ho has examined the effect of TSV scaling on keep out zone (KOZ) and concluded that the near surface stresses degrade the carrier mobility and thus define the KOZ through the piezoresistivity effect. Defining KOZ as no more than 10% decrease in mobility :

• KOZ scales with the square of TSV diameter.

• KOZ minimized at a TSV aspect ratio less than 3
• KOZ is larger for analog devices than digital devices.

• The KOZ can be significantly reduced by using annular TSV.

Victor Moroz – Synopsys / IMEC

Synopsys / IMEC made a presentation on the characterization and modeling of 3D IC with via-middle TSV. Their studies on copper fill chemistries showed that chemistry “C” had 3X the stress of two other comparable materials. This copper had a finer grain structure and showed little to no grain growth after temp cycling.

They found no significant change in TSV C-V behavior before and after thermal cycling. When measuring the minority carrier lifetime from he transient response of a MOS capacitor they saw no significant change in TSV C-V behavior before and after thermal cycling.

After proper thermal treatment to minimize “copper pumping” (copper protrusion) they found no damage to M1 or M2 above the TSV . Examining the impact of TSV generated stress on the transistor performance they found good agreement between modeling and obtained data.

When examining the impact of Cu/Sn microbumps on N-FET logic devices of dies thinned to 25 um , they found a 40% impact on NMOS current due to he underfill that was being used to reinforce the interconnect bumps. Without underfill, no impact on current was observed. The zero stress temp was found to be ~ 160 C , i.e the curing tem of the underfill (as expected). The explanation is that the shrinking underfill bends the thin die around the Cu/Sn bump generating the observed stress.

For all the latest on 3D integration and advanced packaging stay linked to Insights From the Leading Edge……





IFTLE 47 IBM 3D Cooling, TSMC Pkging, UMC 3D Equipment, the CIS Mkt Growth

IBM water cooled 3D IC At the recent CeBIT Fair in Hanover Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM 3D Chip Stacking Project developed at IBM Research – Zurich. Merkel asked him, "Did you take that from Intel?" Palmisano reportedly reply, "No, ours are better”.

[Merkel gets points for pushing IBMs hot button (probably unknowingly) and Palmisano gets points for a sharp response under pressure !]

German chancellor Merkel and IBM’s CEO Palmisano

Their 3D chip stacks are cooled by 50 um micro channel cooling technology . Such liquid cooling reportedly reduces power consumption or the normal cooling fans. The cooling technology was developed by IBM together with the École Polytechnique Federale de Lausanne and the ETH Zurich within the scope of the European CMOS AIC project. Dr. Bruno Michel manages the Advanced Thermal Packaging group at IBM Research - Zurich. The group has pioneered energy-efficient hot-water-cooling and the concept of a zero-emission data center.


The first goal is reportedly to directly stack memory onto the processor. IBM's 3D technology is reportedly scheduled to appear in its upcoming Power8 processor, planned for 2013, using 28 or 22nm process technology. While the technology is reportedly being transferred to iDataPlex servers, it is expected that it will be a few more years before it is fully ready for production.

TSMC Interposer Production in 2012, Making Move into Advanced Packaging

We first started tracking TSMC’s San Jose spring technical symposium in 2008 when TSVs first appeared on their roadmap [ see PFTLE 30, “Foundry TSVs Are a Comin’ – TSMC Makes Their Play for a Bigger Portion of the Pie” In 2009 they reconfirmed their plans for fab based TSV . [ see PFTLE 73, “ TSMC Reconfirms Plans for Fab-Based TSV “]. At this years meeting, last week, Sr VP of R and D Shang-Yi Chiang indicated that they would initially offer silicon interposer technology, which they are currently sampling and plan to have in full production by late 2012.


Perhaps more interestingly, TSMC updated the audience on a theme they first brought up in 2008 when they suggested that they might “in the future” be after a bigger portion of the packaging pie. We recently reported that TSMC would enter the interposer technology and that in fact they were delivering the interposers to Amkor for assembly already bumped, rather than have Amkor do the bumping [ see IFTLE 43, “IMAPS Device Packaging Hilights – 3DIC”] TSMC first put in bumping capacity for 200 mm wafers in 2001 when they installed 15K wafers/mo capacity for business with Altera. They have had limited bumping and WLP capacity since then although they have mainly used their OSAT partners for such operations.


Now TSMC is expanding its bumping efforts. They will ramp up a new 200,000 to 250,000 wafers per month bumping facility in Tainan, are qualifying 100-micron bump pitch lead-free and new copper pillar bump technology at the 28-nm node and are ramping up 28 nm WLP qualification by December targeting the mobile market. Although claiming to still be a “front end company” it is clear to IFTLE that TSMC is making inroads into the packaging business.


UMC Announces 3D Equipment Aquisition


In mid 2010 UMC announced their 3DIC alliance program with Elpida and Powertech Technology (PTI). [see IFTLE 8, “3D Infrastructure Announcements and Rumors” ]At that time, UMCs CTO reported that they expected to be sampling 3D IC solutrions using their 28 nm technology “..in mid 2011) with production slated for 2012. In keeping with these previous announcements, UMC has just announced that they have acquired $19 MM worth of 3D TSV production equipment from Hong Bao Technology (a 73% owned subsidiary)


CMOS image sensors continue to overtake CCD



i-Supply reports that in 2011 CIS ( a key applications area for TSV and in the future 3D IC stacking) will surpasses CCD by > 10:1 in both units and revenue.

Image sensor Shimpents and Revenue (i-Supply)

CMOS image sensors for digital cameras, the last bastion of CCD technology, are expected to exceed those of CCD devices in 2013. CMOS sensor advantages include lower power consumption, reduced cost and circuit integration. The lower power consumption of CMOS sensors yields longer battery life. CMOS sensors also allow for the possible inclusion of on-chip peripheral circuits, increasing the integration of electronics and reducing the size of DSCs. CMOS sensors also support backside illumination technology (BSI), enabling better quality imaging in low lighting conditions.


CMOS image sensors shipments for DCS are projected reach ~ 71 MM units, up from ~ 30MM in 2010. CCD shipments are expected to decline to ~ 67 million units in 2013, down from ~ 94MM in 2010. By 2014, more than 85MM CMOS are expected compared to 51MM for CCD.

Digital still camera image sensor unit shipments by technology (MM of units).

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE………………………..






IFTLE 46 3DIC at DATE 2011; Intel’s Paniccia Points to Optical Interconnect ; Applied Continues Move into Packaging

DATE (Design, Automation, Test – Europe) was held in Grenoble Fr March 14-18.


Penn State
Yuan Xie from Penn State and IBM collaborators from the System and Technology Group took a look at 3D IC thermally-aware bus optimization.
Given that :
- TSVs are clustered for both signal and power delivery
- TSVs are duplicated (redundancy as high as 20x) for higher reliability and higher yield
What is the impact of these TSV clusters on 3D thermal profile ?

They found that large copper TSVs improve the vertical heat dissipation whereas dense and insulated tungsten via farms act as lateral thermal blockage. With the proposed TSV bus optimization flow the peak temperature can be reduced as much as 18.5K and the average temperature reduced by 4.3K.

Technology Design Forum 

The Tech Design Forum ( formerly EDA Tech Forum), has been restructured to focus on fast-growing technology markets in specific regions and has added panel discussions of industry and media experts, as well as technical sessions. They will hold the following meetings in 2011:


March 10 - Santa Clara; April 11 - Tel Avivl; July 20 - New Delhi; July 22 - Bangalore; August 25 - Tokyo; August 31 - Shanghai; September 6 - Beijing; September 8 - Hsin-Chu; September 8 - Santa Clara.


The March 10th Tech Design Forum "EDA Edition" focused on IC Design and Verification, exploring ecosystem networking and increasing competiveness in IC and system product development. The keynote by Dr. Mario Paniccia, Intel Fellow, titled "Bridging Photonics and Computing" discussed recent advances in silicon photonics, including the first silicon photonics optical link operating at 50 Gbps, the scalability of this technology and its potential applications.


Intel asks the question “With all the data that is moving and will need to be moved, how do we connect all these devices?

Paniccia claims that copper is approaching its limits and that optical transfer, which is now mainly used for longer distances, needs to be driven to higher volumes and lower costs to offer a solution for this market .



They feel this will be achieved first by integrating all the devices on to silicon and then by creating monolithically on a silicon base.

Applied Continues Move Into Advanced Packaging

We have previously discussed what appears to be the planned move of Applied Materials into the IC packaging space [ see PFTLE 72, “Samsung 3-D ‘Roadmap’ That Isn’t”; PFTLE 41, “3D Integration Stays HOT at Semicon West” ]


Applied Materials has now signed an agreement with Singapore’s Institute of Microelectronics (IME) to set up a Center of Excellence in Advanced Packaging in Singapore. The Center, to be located at Singapore’s Science Park II, will focus on new capabilities in advanced packaging. When finished, this advanced semiconductor packaging RandD facility will enable IME to support Applied Materials’ product development initiatives. The Centre will have a full 300 mm line of Wafer Level Packaging (WLP) and 3DIC processing equipment and will conduct research in semiconductor hardware, process, and device structures.


Applied expects many advanced logic devices at the 40nm and below technology nodes to be packaged at the wafer level. Russell Tham, Regional President - South East Asia, said, “This collaboration is to …. (bring) our development activities closer to our customers in Asia.”

For all the latest in 3D IC and advanced packaging stay linked to IFTLE......




IFTLE 45 Interconnect Giants

I recently read of the passing of Dimitry Grabbe and it saddened me deeply. As time passes those that preceded us are often forgotten and their accomplishments overlooked.


The Grabbe obituary indicated that he was 83 and had most recently taught at Worchester Polytech in Mass. He was responsible for more than 500 patents in the areas of machine design, semiconductor packaging, electronics assembly and optoelectronic connector design. Dimitry joined AMP in 1973. He was recognized by AMP with a Lifetime Achievement Award, and by the American Society of Mechanical Engineers, which chose him for its Leonardo da Vinci Award. An IEEE Life Fellow, Grabbe was also a fellow of IMAPS.
In 2007 Grabbe was the fifth recipient of the IEEE Components, Packaging, and Manufacturing Technology award. His citation reads: "For contributions to the fields of electrical/electronic connector technology, and development of multi-layer printed wiring boards."


Dimitry was part of the group Microelectronic Interconnect Greats that lived in the greater NYC metropolitan area in the days before Silicon Valley. When I was still young and impressionable, Dimitry was already a highly respected “leader of the Pack” along with close friends Jack Balde of ATT (who passed away in 2003) and George Messner of AMP AKZO (who passed away in 1996). With Bell Labs in its “hey day” and IBM Yorktown up the river, some would say that metropolitan New York was the center of the microelectronics universe.


What separated these three from the rest of the professionals in the area was that they always had time for discussions with younger colleagues like myself. They understood their responsibility to set up and lead meetings on the topics of the day and to help generate the next generation of technical leaders. They were true scientists who had little respect for “managers” and were always ready to share information with all those who would listen. If there was a rumor anywhere in the industry they knew it !


Some of the greatest meetings I ever went to were local meetings held at the old IEEE headquarters near the UN building in NYC . Grabbe and Messner and Balde were always there learning new things and sharing what they knew. A native New Yorker myself, I was living in Boston at the time and would make up excuses to get to NY to attend these meetings and be around these giants. Grabbe kept a museum of electronic products in his barn in PA. Supposedly he had things in there that no other museum had. Professionals from all over the country were sending him electronic devices knowing that he would take care of them in his personal “museum”. I truly hope all of that has not been lost ! Maybe an IEEE museum in his name would be appropriate? Many colleagues knew that both Messner and Grabbe had immigrated from the old Soviet Union after WWII. Grabbe related to me many times that he had had some problems with the KGB and spent the rest of his life “packing” …not packaging…but "packing" in the urban context of carrying a handgun in a shoulder holster. For those who did not know this – it was the reason he always kept his jacket on !


In the early 1992 I got the opportunity to edit the first MCM textbook “Thin Film Multichip Modules” with Messner, Balde and Motorolas Iwona Turlik. A great learning experience on how to assemble and share information. (Little did I know what I would be doing later in life)

A young Garrou, Iwona Turlik (Motorola), Messner and Balde at the publication of the book Thin Film Mltichip Modules

Grabbe and Balde also share the fact that they have received the IEEE CPMT Society medal, the highest honor available for packaging and interconnect practitioners. It’s worth looking at the list of winners of this award since these are truly the giants in our packaging field.


2004 – Jack Balde – ATT


2005 – Yutaka Tsukada - IBM


2006 – C. P. Wong – ATT, Ga Tech


2007 – Dimitry Grabbe – AMP


2008 – Paul Totta, Karl Puttlitz - IBM


2009 – George Harman – NIST


2010 – Herbert Reichl – Fraunhofer IZM, Berlin


2011 - Rao Tummala - IBM, Ga Tech


If anyone reading this does not know who these men are or why they won these awards…well you’ve got some reading to do !


For all the latest on advanced packaging and 3D IC technology stay linked to IFTLE…

IFTLE 44 JEDEC Standards, Hynix moves on 3DIC and IC Power Rankings

JEDEC ANNOUNCES 3D-IC STANDARDS DEVELOPMENT
JEDEC has recently summarized their ongoing standards development work related to 3D-ICs. The following JEDEC committees and task groups are engaged in developing 3D-IC standards:
Memory:
- the Solid State Memories Committee (JC-42) has been working since 2008 on definitions of standardized 3D memory stacks for DDR3 . Future DDR4 standards will be implemented with 3D input.
- the Multiple Chip Packages Committee (JC-63) is currently developing mixed technology, pad sequence and device package standards.
- a Low Power Memories Subcommittee (JC-42.6) task group is developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on SoC Processors.
Quality
and Reliability:
- the Silicon Devices Reliability Qualification and Monitoring Subcommittee (JC-14.3) is working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions.
- reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
Packaging :
- the Mechanical Standardization Committee (JC-11) has been working since 2010 on Wide I/O Mobile Memory package outline standardization, including a task group focused on design guide creation.
JEDEC invites interested companies and organizations to participate.
I have previously expressed my concerns over the lack of transparency in JEDEC standards due to their self imposed rule forbidding revealing authorship [companies and /or individuals] up the standards. [ see PFTLE 128 “3D IC Standardizatio Begins” ] Those concerns still stand.

Hynix Semiconductor Joins SEMATECH's 3D Interconnect Program
Hynix the last top 5 DRAM to not have announce plans for 3D IC has become a member of SEMATECH's 3D Interconnect program. Dr. Sung Joo Hong, Head of the R and D Division of Hynix Semiconductor commented that "3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction,….by joining SEMATECH's 3D Interconnect program and collaborating with industry-leading partners, we expect to play a critical role in accelerating the commercialization of wide I/O DRAM…” Hong reported that Hynix and SEMATECH will address the commercialization challenges facing the industry as it commercializes wide I/O interface structures using TSVs in high volume manufacturing in the next two years.Hynix will be working with IBM, GlobalFoundries, Toshiba, Samsung, Applied Materials, Tokyo Electron, ASML and Novellus as part of the SEMATECH program.

IC Power Rankings from IC Insights



Semiconductor industry capital spending is becoming more concentrated, with a greater percentage of spending coming from a shrinking number of companies. As a result, IC industry capacity is also becoming more concentrated, and this trend is especially prevalent in 300mm wafer technology.


IC Insights has created a “Power Rating” which is determined by each company’s 300mm wafer capacity and its rank in capital spending.

Overall, IC Insights believes that the top-10 companies in the “Power” ranking will be the primary drivers in adding capacity over the next few years. GlobalFoundries and TSMC get a boost from their currently aggressive capital spending plans and are very likely to add a significant amount of 300mm capacity over the next few years. Among companies ranked between 11 through 22 Renesas, IBM, TI, ST, and Fujitsu are moving to or continuing with a fab-lite strategy. These five companies appear unlikely to add new 300mm capacity in the future. Powerchip, SMIC, ProMOS, Winbond, and Xinxin appear limited by financial where-with-all (e.g.,) or a lack of desire (e.g., Rohm and Panasonic) to add significant amounts of 300mm capacity to produce leading-edge digital ICs.



With only ten major players in the 300mm capacity space, the customer base for leading-edge IC production equipment has become very narrow. It is likely that IC equipment and materials suppliers will be focused on these 10 companies in the future.


For all the latest in 3DIC and advanced packaging news and conference updates stay linked to IFTLE…