The IEEE Int Test Conference (ITC) held in Austin in November had a full-day tutorial, several technical papers, and a panel session, all on 3D-TEST. This was followed by a dedicated 3D-TEST Workshop, the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits “3D-TEST” which was chaired by Yervent Zorian of Virage Logic and Erik Jan Marinissen of IMEC. No one can any longer say that the industry is not focused on addressing 3D test.
Zorian
Marinissen
The technical program consisted of: an Opening Keynote by Bob Patti of Tezzaron); an Invited Address by Brion Keller of Cadence; invited talks by Synopsys, ARM, IMEC, Qualcomm, Avago Technologies, ST-Ericsson, and Texas Instruments and technical papers from Cascade Microtech, Virginia Tech, Fraunhofer, TU Delft, NCSU, Mentor Graphics and, TSMC. The conference had financial support from Advantest, ARM, Intellitech, Mentor Graphics, Scanimetrics, Synopsys, SynTest, Tezzaron , and Tokyo Electron.
IEEE Computer Society 3D Test Standardization Group
Marinissen presented the early results of the IEEE Computer Societies TTSC Standardization study group on 3D Test. Most of the major players are participating
The following standardization needs have been identified:
Tezzaron
Bob Patti once again reiterated that the killer application for 3D IC will be what he calls “split die”, i.e. removing embedded memory from SoC and bonding it directly to the logic chip as shown below.
Tezzarons form of BIST is called Bi-STAR™ by Patti, who claims that it “..tests and compares 2304 bits/clock cycle; more than 100 times faster than can be achieved by any external memory tester” Reportedly Bi-STAR can test and repair:
• Bad memory cells
•Bad line drivers
•Bad sense amps
•Shorted word lines
•Shorted bitlines
•Leaky bits
•Bad secondary bus drivers
•Bad CAMS
Cadence
Sanjiv Taneja of Cadence lists the following as Design and Test Challenges
• Front-end design
– Logic synthesis with 3-D partitioning
– Logic synthesis with 3-D physical awareness
– 3-D design/timing/power constraints
– Equivalence checking across multi-chip RTL/netlist
• Physical design and analysis
– 3-D floorplanning and partitioning
– Thermal/TSV-driven placement
– Global and detailed routing with TSV
– Parasitic extraction with 3-D electrical modeling
– IR drop and thermal analysis with TSV, Silicon interposer
• Chip-package co-design
– 3-D connectivity checks and constraint management
· Test Challenges
– New defect types (defects due to thinning, TSVs)
– TSV Interconnect defects
– Limited test access with challenges similar to SiP
– Redundancy and repair of TSVs
– Key Technical Requirements
• Ultra-low pin count compression
• Reduced Pin Count Test
• Pattern Fault model
• 1149.1/1500 support
• Creation of KGD after wafer test
• A means to test the TSV interconnect between stacked die
• A means to test inside the die of the stack
Cadence points to the integration of design and test as the only way to solve these complex issues and that concurrent optimization for area, timing, power and testability is the only means to achieve required predictability.
Cascade Microtech – Probing of TSV at 40 um pitch
Ken Smith of Cascade Microtech indicates that contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards can achieve.
Smith claims that there is no known physical roadblock to scaling basic card mechanics to much smaller dimensions. To reduce the probe pitch by a factor of k, the basic scaling required is to reduce all of the probe’s dimensions by k, along with maintaining constant pressure at the probe tip.
Cascade claims their high-density MEMS probe card technology make 1 gram tip forces feasible and very low pad damage possible at 40 micron array pitch.
In order to minimize pad damage, it is desirable to probe at the lowest force range that yields stable contact resistance. Contact resistance is a function of probe tip size, shape and metallurgy; probing force (pressure); substrate metallurgy; test current level; and contact cleanliness (determined by the cleanliness of the probe tip, DUT surface, test environment as well as the cleaning regimen).
Smith claims that “..the measured results to date indicate successful scaling of mechanical probing to array pitches of around 40 um. Practical probe cards are capable of 40 um pitch and tip forces below 1 gm. These lithographically fabricated probe cards enable scalability to lower cost just as IC linewidth scaling has reduced the cost of IC functions. Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe is roughly proportional to the probe area”
Smith reports that pad damage at these low forces is extremely small with scrub marks less than 100 nm deep.
We will continue our discussions on the 3D Test Workshop in the next blog including an exclusive photo of the IEEE 3D Test with a surprise model !
For all the latest on 3D IC Integration and Advanced Packaging stay linked to IFTLE…..
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