IFTLE 4 Are We All Suffering From 3D Stress ?

According to Geert Van der Plas of IMEC ”..TSVs, die thinning, bonding and (flip-chip) packaging result in a 3D chip-stack with built-in stress which can potentially lead to yield, electrical performance and reliability issues”

To address these issues, SEMATECH held a workshop on “Stress Management for 3D ICs” on March 16, 2010 in Albany, NY. Thanks to old friend Larry Smith for sending the pertinent info from this conference to share with you.

Synopsys

Xiaopeng Xu detailed the use of the Synopsis TCAD software to analyze 3-D structures [ link ]. The different modules in TCAD can not only be used to extract 3-D R,C & L but can also predict interconnect stress distributions from multiple stress sources and reportedly detect stress hot spots that are susceptible to debonding, voiding and cracking.

The presence of TSV appears to create more impact on the mobility of p doped Si than n doped as shown below.

Their data shows that larger TSV diameter leads to larger mobility change in Si due to larger deformation and shear stress as shown below.

Also of significant interest is the data which reveals that low-k dielectric with its inherent lower modulus results in less resistance to copper extrusion.
On Mar 09, 2010 Synopsys, and IMEC announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs).

Ansys

Kamal Karimanal of Ansys looked at techniques applicable to TSV based 3D packaging. AN example is the use of ANSYS Icepak Software to examine metal distribution and calculate temperature variations across the stack.

Qualcomm

Riko Radojcic of Qualcomm pointed out that stress management was important because for 3-D it becomes the sum of the on chip strains + the normal chip package interactions and the new 3-D TSV issues such as:

- interaction of (big) Cu TSV and surrounding devices
- µ-Bump issues with Tier 1 and Tier 2 die
- thin Si : Enhanced BEOL-FEOL + Si-package CTE Mismatch
- backside RDL : new CTE Mismatch challenges
- die to die : stress re-distribution among the stacked die
- die alignment : stress concentration among stacked die

He points out that we currently manage this on 2D chips through design rules and that it is these design rules that must be extended to 3-D stacks such as:

- Keep Out Zone Rules
- No change to device characteristics vs. ‘normal 2D Si (all devices)
- Die Stacking & Alignment Rules
- No incremental CPI effects for T1-T2 and T1-Package Interactions
- PAD and CUP Rules for µ-Bumps
- No CPI or Performance impact on either T1 or T2

Radojcic proposes an EDA solution “ that bridges package and Si design and simulation environments without forcing re-tooling from incumbent solution in either domain”

IMEC

Geert Van der Plas of IMEC indicated that insight into 3-D IC thermo-mechanical behavior requires analysis of test structures such as those shown below.





For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE……

IFTLE 3 ......on Finding the Beef & Finally Addressing 3-D IC

This week we will catch up on some info about ALLVIA and Novellus that should be of interest to all those watching the 3-D IC evolution.

ALLVIA

To be frank with you (which you know I always try to be) I wasn’t a fan of the press releases by ALLVIA back in the winter and the resulting news stories derived from them [ for instance see: “ALLVIA offers New TSV Reliability Data”, Semi Int 01/25/2010 ].

My “beef” was “Where’s the beef ?”

[ For those of you reading this outside the US, yes I’m launching off into another of my play on words here. Several of you have asked me, when we met at conferences, to help you out when I use these play on words - so I will do now. The term “my beef” is a slang term used as a synonym for “my complaint” or “my problem”. “Where’s the beef” is a famous US television advertising quote meaning literally “where is the meat ?” The original TV commercial in 1984 featured a grey haired grandmother opening a competitors large hamburger bun, seeing a very small portion of meat and saying into the camera “Where’s the beef” (see below) ]

The headlines such as “TSV foundry ALLVIA recently completed full reliability testing of its TSVs” and “..the company is now making the data available...” led me to believe that reliability data was being disclosed but none was to be found in the “news” stories I was reading.

No indication of what was built, no indication of what tests were run and no indication as to the results of said reliability tests. Interested parties were told to contact ALLVIA. My conclusion was “Nice eye catching headline – but WHERE”S THE BEEF”, in any of the storiess that were based on this press release.

In mid March Allvia offered a webcast entitled “Silicon Interposers with TSVs and Thin-Film Capacitors”. Knowing Sergey and his team, I was willing to give them “the benefit of the doubt” .

I’m not sure how many viewers the webcast attracted, but I was in attendance, seeking "the beef", and I’m happy to say I received the data I had been looking for. I was even more sure that I had done the right thing by passing on the “headlines” in January (unlike so many others) and waiting until I had “the beef” to share with you, my readers.

This blog was then entered into que at PFTLE, but as we all know ,factors beyond my control delayed its publication until now.

So after that long introduction, lets take a look at what ALLVIA has to offer because it is still pertinent and interesting information for all of us that are interested in 3D IC.
.
As you may know, ALLVIA is currently housed in Sunnyvale where they have 6000 sq ft of clean room. This past winter they announced the acquisition of an additional 60,000 sq ft of clean room at a manufacturing facility in Portland OR. Their capability summary is detailed below. With a TSV sweet spot of 30 – 150 um they are obviously focusing on vias last-backside and interposers.

Allvia appears to be looking at the market segment that currently requires very high density laminate packages, such as Endicott Interconenct supplies, which are high density, high quality, high performance and high cost. ALLVIA claims they “...avoid the huge substrate cost increase by using a sophisticated silicon substrate on top and a cheaper organic substrate on the bottom.” Such hybrids solutions “...may cost a little bit more, but are less expensive than most non-hybrid advanced organic substrates" claims Sarastiouk.

They have examined thermal cycling of their TSV . Some of the results are shared below.

ALLVIA is also offering thin film capacitor technology integrated onto their interposers.
Reliability results for Si interposers mounted on BT substrates are shown below.

ALLVIA claims they are now ready for scaling to volume production. Good luck to them in this endeavor.


Novellus – Finally Putting 3D IC in their sights

When looking at the ECD (electrochemical deposition) landscape in relation to 3-D IC, the names Semitool, Nexx and Ebarra come to mind. They are attending 3-D conferences, making 3-D presentations and are engaged with customers on 3-D scaleups. When you look at this list one big copper plating player is noted by its absence – Novellus. Their equipment offerings include PVD and CVD Cu and W solutions and well as Cu plating technology. Their ECD copper tool “Sabre™” was one of the first on the market to meet the demands of dual damascene copper 12+ years ago.

I’m now glad to tell you that this lack of focus on 3-D IC seems to have been reversed in the last several months. Last July Novellus and the University at Albany’s College of Nanoscale Science and Engineering (CNSE) announced that they had formed a $20M partnership to conduct next-generation R&D into sub-22nm semiconductor manufacturing technology. As part of the agreement, Novellus will install three advanced thin film deposition tools-a VECTOR® plasma-enhanced chemical vapor deposition system (PECVD), a SABRE® copper electrochemical deposition system, and an ALTUS® tungsten chemical vapor deposition (CVD-W) system-at CNSE complex. It was announced that a team of Novellus researchers, located at CNSE, will be conducting leading-edge research into among other things copper fill for interconnects and copper TSV fill for 3-D IC.

On March 9th Novellus announced an advanced copper barrier-seed physical vapor deposition (PVD) process for the TSV market. The process uses Novellus’ INOVA platform to produce highly conformal copper seed films that are reportedly four times thinner than conventional PVD seed approaches. Novellus claims the process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent electroplating step. The ionized PVD process chamber causes a larger fraction of the sputtered film to land on the sidewall, which in turn results in a more conformal deposition. Novellus’ process can reportedly achieve void-free feature fill in a 60 micron deep, 10:1 aspect ratio TSV feature with vertical sidewalls using a 2000 angstrom thick copper seed layer. The conventional PVD approach requires an 8000 angstrom thick seed layer to achieve the same result. The 4X thinner TSV seed layer results in a substantial increase to system throughput and reduces the cost-of-consumables by greater than 50 percent as compared to conventional PVD approaches.

This was followed up a week later with an announced joint development program with the IBM “to design a manufacturing-worthy, copper-based, three dimensional (3- D) semiconductor Through-Silicon Via (TSV) process using Novellus' SABRE(R) copper electroplating and VECTOR(R) plasma-enhanced chemical vapor deposition (PECVD) systems.”

Novellus has reportedly developed a unique, high performance SABRE ElectrofillTM TSV process that uses Novellus hardware and chemistries to achieve void-free fill with minimal copper overburden. Copper overburden is reportedly reduced by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. They also claim that the SABRE TSV chemistries have faster plating times, resulting in higher throughputs.
To address the requirement of lower temperature dielectrics, Novellus' VECTOR platform enables the deposition of stable dielectric films at temperatures <>

In addition, Last week Novellus introduced their XMM technology which is an inline wet etch process to reduce copper overburden on copper fill applications like TSV. XMM technology reportedly prevents chemical attack at the grain boundaries, resulting in a smooth, highly reflective copper surface. In addition, XMM technology reportedly decouples overburden deposition control from feature filling, which allows copper fill and overburden to be optimized sepertely.

With these introductions it is now obvious that Novellus is Focused on 3D IC !

For all the latest on 3D IC and advanced packaging stay linked to IFTLE.........

IFTLE 2 Adv Pkging at 2010 Las Vegas ECTC

As Jack Nicholson said in the great Stephen King horror classic “The Shining”

………………I’m baaack…………………………

Wanting to keep you up to date with recent activities, and yet not loose any of the materials that were in que two months ago when Semiconductor International went under, I will present a quick summary of announcements and rumors at the 2010 ECTC in this blog and follow with some of the blogs that were in que. I will then continue with discussions of key presentations from ECTC which should carry us into mid July and Semicon West.

They say “What goes on in Vegas stays in Vegas”. Not so when we’re talking about 3D IC and advanced packaging…that gets reported here in IFTLE.

IEEE CPMT Takes Over Full Sponsorship of ECTC

The ECTC Conference in one form or another has been in existence since 1950. The joint sponsorship by the IEEE Components, Packaging and Manufacturing Society (CPMT) and the ECA (formerly the EIA) ended last week when IEEE bought out their long time partner. Rolf Aschenbrenner, President of IEEE CPMT commented that “.. this change should be invisible to the attendees and the ECTC program committee. We plan no changes in how the ECTC operates”

[ top l to r: Tom Reynolds, Bob Willis , Rolf Aschenbrenner,

CP Wong, Steve Bezuk, bot: Marsha Tickman, Jean Trewhella, Bill Chen ]

Fan Out WLP taking off

Most of you are familiar with fan out packaging which was developed in parallel, several years back, at Freescale (RCP) and Infineon (eWLB). During the recent hard economic times Freescale scaled back their process work and eventually licensed their process to Nepes. Infineon developed a commercialization consortium with ST Micro, ASE, STATSChipPAC and most recently Nanium (formerly Quimonda Portugal). eWLB wafers have been in mass production on 200mm lines at Infineon, ASE and STATS ChipPAC since 2009. STATS has been aggressively pursuing commercialization [ highlights from the 2010 ECTC] . STATS and Nanium are in the process of scaling up 300 mm lines. SPIL, Amkor, UTAC and others are also developing their own Fan-out wafer level packaging options.

The STATS team is pictured below at their ECTC booth where their eWLB technology was highlighted.

[from l to r: Vic Lozada, Raj Pendse, Flynn Carson, Lisa Lavin and Seung Wook Yoon]

Rumors are circulating that Freescale management, seeing the success that eWLB has been receiving, has revived their RCP process group and are looking to obtain further licenses. Rumors are that Broadcom is looking seriously at the RCP based devices. Talking with STATS who claims yields “..are already in the 90’s” for the 5-10MM units they produced in Q1 2010, it became clear that the reconfiguration step is not as simple as it looks on a power point slide. Molding compound shrinkage requires that the chips be unequally spaced across the wafer before molding compound is applied and cured and the subsequent RDL mask must match this unequal spacing – obviously. Multi die eWLB (i.e SiP ) have been qualified by the STATS team who now have stacked, (two sided) eWLB solutions in development. In any event, fan out WLP has officially taken off and will unquestionably become a major packaging option in the future.

Global Technology Development Focus Remains on 3D IC

I counted more than 25 presentations involving TSV based 3D IC. Although there were no commercial announcements, there was continued steady progress by nearly all the major players in the industry. By the way, I’m seeing more and more use of the acronym 3DIC so when doing lit searches you better use both.

I saw nothing to change my mind that the industry has narrowed process options down to vias middle (from the foundry) and vias last backside (from the OSATS). The latter mainly for devices such as CMOS image sensors which are already in full commercial production at players such as Toshiba, ST Micro and Samsung.

You can be sure that not having a source of chips with vias middle TSV is slowing down product development work. Currently, only those with their own IC fabs can gets chips containing built in TSV. While everyone is awaiting TSMC, Global Foundries and others, there appears to be a significant opportunity for R&D IC lines that can deliver test chips with vias middle TSV for developers to work with. IMEC has shown this capability, but who else out there can make such structures available ??

Please send me your info if you are or could be supporting this need.

ASE focus on 3D IC

It appears that with Cu wire bonding completely installed at ASE they can now focus on 3D IC. I’m told the EE Times article indicating that 3D at ASE was imminent [ASE Breaks Ground on New Packaging Plant] stirred significant activity at the ASE sales offices . Reports to IFTLE indicate that the new building in Kaohsiung (K 15) will indeed be used to bring all 3D equipment together, under one roof. Current D2D and D2W assembly from Chung Lee will be moved to Kaohsiung. BUT….I’m also told by those who should know, there will be no 300 mm 3D instillations till 2011 so commercial 3DIC assembly is unlikely before 2012, if then.

IBM 3D rumors

Last December at the RTI ASIP in Burlingame, IBM confirmed that there was no commercial qualified 3D line running yet. Speculation at the ECTC was that a TSV containing product will be introduced into their server line. Product would come off the R&D line. An announcement will come if performance meets expectations.

TSMC

Recent announcements of their open innovation platform indicates that TSMC is putting the pieces together to enable 3D design [TSMC adds 3D, ESL tp Platform Efforts]. Their design plans will first deal with Si interposers and it will subsequently support full 3D stacking capability. IFTLE conversations with TSMC personnel indicate that their initial roadmap announcements showing vias middle in 2011 was (as PFTLE had predicted) extremely aggressive . They view silicon interposers as a faster solution for their graphics chip customers and will switch them to full 3D stacking later. The fact that long time TSMC partner ASE will not have 300 mm equipment in place till 2011 confirms this conclusion.

3D IC Bonding

There were 10 papers at ECTC dealing with various aspects of Cu-Cu and Cu-Sn-Cu bonding including papers from IMEC, IBM, Leti, Samsung, RTI, Univ Tokyo, Nanyang Univ, / Globalfoundries. As PFTLE noted many years ago, the low COO choice of bonding techology will be limited to choices that result in mechanical and electrical connection at the same time. While the OSATS have been focused on developing Cu/Sn intermetallic technology for 3D strata bonding, there is still significant commercial interest in copper-copper bonding, perhaps due to the lower resistance connections. Cu-Cu bonding comes in white or black i.e. thermocompression or direct bonding. Actually there is enough data out there now that is becoming evident that a continuum exists between the two – shades of grey -which are dependent on the variables of surface finish, temp and pressure. A full blog will be coming up in a few weeks discussing all of this information.

Thin Film Dielectrics

Michael Toepper, Fraunhoffer IZM dielectric expert, discussed thin film polymers to a standing room only crowd and concluded that materials with the highest tensile strength and elongation were best suited for reliable fan in and fan out WLP structures.

Fan out WLP require lower temp curing materials since the chips are embedded in low temperature molding compounds. Most of the practitioners IFTLE is aware of are using JSR ( WPR 5100 series ) which are epoxy novolacs with rubber filler or the new HD Micro low cure temp PBOs ( HD 8900 series ).

The Asahi Glass group (AGC) has focused application work for their ALX polymer on fan in and fan out WLP. This material is in trials at IME, IZM and RTI and looks very promising as a BCB substitute with double the elongation and curing at 190 ◦C.

[Hijiri Kuriyama, Alan Huffman (RTI), IFTLE, Takeshi Eraguchi ]

Coming up soon:
- Finding the Beef and Addressing 3D IC
- Sematech Addresses 3D Stress
- A Date in Dresden

For all the latest on advanced packaging and 3D IC stay linked to Insights From the Leading Edge…………………..

IFTLE 1 Insights From the Leading Edge

Like the Phoenix rising from the ashes Perspectives from the Leading Edge, PFTLE, rises from the internet black hole that it was thrust into to become Insights from the Leading Edge, IFTLE. Not much will change except the blog location. IFTLE will try to bring you weekly insight into the technical and business comings and goings in the 3DIC and IC packaging segments of our microelectronics community.

First a little background on what happened. Unbeknownst to me, Reed Elsevier the owner of Semiconductor International, owned a portfolio of magazines with a broad reach of topics. When the board decided to exit the magazine business they decided to simply close down many of them. Thus on April 16th I received a message from "headquarters" thanking me for my activities with them and terminating me and all the rest of the Semiconductor International staff. After a few seconds of shock I contacted Aaron Hand (Editor) and Dave Lammers (News Editor) and received confirmation that, indeed, Semiconductor International was no more.
I quickly tried to get back onto the web site to add some verbiage to let all of you know what had happened and tell you that I would be looking for another site to host PFTLE, but alas, I had been locked off the web page (no hard feelings, I'm sure I would have done the same thing if the situations were reversed). Having worked for a 25+ billion dollar company for most of my career, I had watched many a "big dog" get escorted off the company grounds after being told that they were terminated ....that’s simply the way it is done. Two weeks later and the web site semiconductor.net was closed and links to 3 years worth of my material now pointed into a black hole !

Emails from friends and readers began coming in questioning what was going on and pointing out that their links to my stories and blogs were now pointed no where.

The good news is that while the blogs are legally "work made for hire", my contract allows me a "worldwide, perpetual license to publish , display and distribute the works after 3 months of exclusivity". So I'm in the process of reloading the 128 blogs. By your readership of 7000 - 10,000+ hits per month, I think many of you would agree that these blogs contain a lot of worthwhile information that all of us would like to continue to access.

I will continue to refer back to these in IFTLE, and will give you all the URL to the site as soon as everything is locked down and tested. The plan is to index these so you will be able to access any and all information about a given company or topic from this new web site.

I have decided to join forces with Solid State Technology. Editor Pete Singer, while with Semiconductor International , was actually the person who gave me the opportunity to do all of this back in the summer of 2007. I look forward to working with Pete and his competent staff as IFTLE moves forward.