Somehow IFTLE missed detailing the actual product technology release of the Sony ISX014 (link) at the ISSCC earlier in the year. This is important enough in terms of 3DIC product introductions that we will cover it now.
The Sony ISX014 8MP sensor features 1.12um pixels and
integrated high speed ISP.The pixel layer and logic layer part are manufactured
as separate chips and stacked by using TSVs. Previously the pixel and logic
circuit of Sony's back side illuminated
(BSI) CMOS image sensor were formed during the same fabrication process. This
is compared below.
Actual layers are shown below:
Using
separate pixel and logic layers allows the use an optimal process technology
for each separate layer. Sony fabricated the pixel chip and logic chip using
90nm and 65nm process technologies, respectively. Stacking the chips, reduced
chip area by 30%, compared with the previous image sensor made using 90nm
process technology.
TSVs
are used connect the row drivers on the pixel chip with the row decoders on the
logic chip and connect the comparators on the pixel chip and the counters on
the logic chip. TSVs are formed in areas to reduce the influence of noise. For example, comparators are arranged on the
pixel chip, which can be manufactured by using Sony's matured process
technology, rather than on the logic chip.
The
stacked vs conventional technologies are compared below:
Since
the logic chip can be manufactured at Si foundries, Sony does not have to
invest in advanced logic process technologies.
Sony
is in volume production of the new CMOS image sensor for its smartphone, other
companies' tablet computers, etc. The size, pixel count and pixel pitch of the
sensor are 1/4 inch, 8.08 million and 1.12μm, respectively. Characteristics of the CMOS device are
shown below:
Sony
has not disclosed details on TSV processing. The total number of TSVs is a few
thousand. The
following figure shows the stacked chips cross-section.The
insulators of the upper and lower chips are attached together. It seems that
TSVs are formed later to connect the circuit layers of the chips. IFTLE assumes they are using the Ziptronics oxide
bonding technology that they licensed previously [ see IFTLE 65, “Samsung’s 32GB RDIMM DDR3, GLOBALFOUNDRIES Packaging Alliance, ZiptronixLicensing News”.
A recent cross section produced by chipworks helps us
understand the interlayer connections done with 6um pitch TSV [link].
IFTLE would expect other CIS manufacturers to move in this
direction shortly.
For all the latest in 3DIC and advanced packaging stay
linked to IFTLE……………………………….
Coming soon:
- An end of year update from Lester the Lightbulb - more on IMAPS 2013
- more on the GIT Interposer Workshop - coverage of IWLPC
- more on IEEE 3DIC - coverage of RTI’s 3D ASIP
- Christmas coverage of Hannah and Madeline
