IFTLE 52 3D and Adv Pkging at ICEP 2011 and reschedule of 2011 3DIC (Japan)

ICEP
The ICEP [ Int Conf on Electronic Packaging] is put on by JIEP (Japan Institute for Electronic Packaging) It is usually held in April every year during cherry blossom time in Japan. I recall that in 1998,when the meeting was known as IMC/IEMT Rao Tummala and I were in attendance. At the “gala reception” we were coerced into joining the entertainment on stage and then I, as the junior member, was further coerced to dress up in a “happy coat” which my granddaughters now know as grandpa’s samuri outfit. (see below).

At this years conference, John Lau of ITRI gave an excellent invited review on the origins, status and future prospects for 3D IC which includes a must have list of 140 references in the field including his observation that Shockley, inventor of the transistor, actually patented TSV in 1958.

Lau astutely observes “… using a passive interposer to integrate a few “bullet proofed” chips together (like a MCM) want and are used to doing. The passive interposer becomes the most effective 3D IC integrator. It could be very low cost because we don’t have to dig and fill the holes on the active die. Also we don’t have to thin and metallize the active die. Furthermore we don’t have to temporarily bond and debond a supporting wafer to the active wafer.”

In another paper Lau and his ITRI colleagues discuss the feasibility of 3D IC for system in package structures. In their test vehicle a assive interposer supports a 4 memory chip TSV stack, an electrical test chip, a thermal test chip and a mechanical test chip to measure stress and warpage . The interposer is 12.3 x 12.2 mm and 100 um thick. The TSV diameter are 10 and 15 um on 40 And 50 um pitches.

TC Chang from IRTI detailed the use of thermocompression bonding for the joining of Pb free microbumps on 20 um pitch. Solvent and plasma are used to remove the flux residue between he microgaps and a capillary underfill with 0.3 um filler (Namics) is used to fill the gaps.

NEC, Univ Tokyo and ASET reported on the formation of power regulators (buck converters) which consists of a CMOS LSI including active components and an output filter embedded in the Si interposer.

Koyanagi and co-workers at Tohoku University described their development of 5 um diameter backside TSV technology. Tohoku is located very close to the site of the Tsunami devastation so I’m sure we all wish them well as they bring their University and their 3D activities back up to speed.

To develop 5 um backside TSV the chip was supported on a glass or silicon support substrate and thinned down to 15 um by grind and CMP. ~ 1 micron SiO2 was deposited as an isolation layer / hard mask . The TSV were created with Bosch process and then lined with SiO2 (500 nm) . Etching parameters (shown below) were used to control the scallop. The bottom of the insulated TSV were opened by SiO2 etching using the thicker backside oxide layer as partially sacrificial mask for the etching.

2011 IEEE 3DIC

The IEEE 3DIC meeting which was scheduled for Tokyo this fall has been moved to Osaka in Jan 2012 due to the tsunami / nuclear disaster that Japan has been recently dealing with. The submission deadline for abstract is September 30, 2011.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….

IFTLE 51 2011 IEEE IITC 3D Highlights, and IEEE ECTC OSAT Preview

The annual IITC, sponsored by the IEEE Electron Devices Society was held a few weeks ago in Dresden. Ehrenfried Zschech of the Fraunhofer , John Iacoponi of GLOBALFOUNDRIES and Takeshi Furusawa, of Renesas lled the program committee.
The conference which was instituted in the mid 1990’s was the premier show dealing with issues of on chip interconnect, especially low K. In recent years it has shifted some focus to 3D integration [ see PFTLE 37, “IITC on the 3D Integration Bandwagon” and IFTLE 10 IFTLE 10 “3D at the IEEE IITC”.

In this years conference Yann Civale from IMEC shared technical details on the “Thermal Stability of Copper Through Silicon Via Barriers during IC Processing”. The IMEC via-middle process flow results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. As you may recall this was introduced to reduce the impact of copper extrusion [ see PFTLE 125, “ 3-D IC at Ft McDowell” and IFTLE 34 “ 3D IC at the 2010 IEDM”] Thus, it is essential to determine the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. IMEC reports that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

Paul Marchal of IMEC presented a “Technology Roadmap and Status” for 3D IC. Marchal indicates that 3DIC technology is now becoming available, that co-optimization of design and procfess technology are required and that one of the remaining hurdles remains mechanical and thermal stress.

The thermo and Thermomechanical challenges for DRAM on Logic are shown below.

Interestingly scaling of the TSV diameter will strongly reduce the KOZ (keep out zone) as shown below.

The combination of microbump and underfill has been identified as the major contributor for stress on thinned die as the shrinking underfill bends the thin die around the microbump. Agreement salso needed on exchange formats and models are required.

Projections for 2015 include:

- Silicon wafer thickness : preferably 50 um and holding due to stress and thermal issues.

- Microbump pitch : 20 um and decreasing for improved electrical specs

- SV dia / pitch : 5-3 um / 20/10 um and decreasing dia scaling to decrease KOZ, results in AR ~ 20

Armin Klumpp Peter Ramm and co workers at Fraunhofer EMFT presented their information on  “Reliability testing and Failure Analysis of 3D Integrated Systems“. Their 3D-integrated reliability test chip is a 3-level-stack with a modular layout so several types of stacked devices can be realized, numbered type 1 – 4 with basic functions of the “Bottom”, “Middle” and “Top” layers in the figure below. The larger size of the Bottom chip allows access to the measurement pads, independent of the number of stacked layers. The medium chip having TSV’s and can be tested already in the stage of thinned silicon with the appropriate metal layers on front and back side (type 1). In combination with the bottom chip daisy chains can be realized that include TSVs and assembly pads (type 3). Medium chips with no TSVs, can be tested (type 2), to be able to distinguish between TSV and assembly pad parameters. Type 2 and type 3 are available in parallel as soon as the medium chip is assembled on the bottom one. Adding the top chip forms a three level stack (type 4) with daisy chains including TSVs and two levels of assembly pads. The medium chip serves in this case as feed through for electrical signals. The top chip shortens the electrical path to form a daisy chain consisting of at least two TSVs. The chip lay-out contains several elements including Kelvin structures, DC and RF test structures, daisy chains and TSV’s with dimensions varying from 3-50 um. 3D-integrated test chips were fabricated by application of Fraunhofer EMFT´s TSV SLID technology. The applied 3D TSV process is based on inter-metallic compound (IMC) bonding and TSV formation before stacking. For reliability testing, termal cycling (-55 C° to +150 °C) was performed and additional analysis was done by cross sectioning and plasma-FIB.

ECTC Preview

Remember when we all rushed to ECTC anticipating the latest advanced packaging presentations of IBM, Intel, Bell Labs and NEC, Hitachi and Fujitsu ? Well times have changed, and over the last two decades the pendulum has swung towards the OSATS and I think it’s fair to say that Amkor, STATSChipPAC and ASE are now producing more than their share of outstanding papers at every ECTC conference.

As an example, here is the list of papers that Akor is scheduled to present next week in Orlando.

"Cu Pillar and µ-bump Electromigration Reliability Comparison with High Pb, SnPb, and SnAg Bumps" presented by Ahmer Syed

"Advanced Coreless fcBGA Package with Embedded High-Dk Thin Film Decoupling Capacitor" presented by GaWon Kim

"Next Generation Fine Pitch Cu Pillar Technology – Enabling Next Generation Silicon Nodes" presented by Curtis Zwenger and Mark Gerber of TI

"Issues in Fatigue Life Prediction Model for Underfilled Flip Chip Bump" presented by Ahmer Syed

"Crack Initiation and Growth in WLCSP Solder Joints" presented by C.J. Berry

"A Study on an Ultra Thin PoP using Through Mold Via (TMV) Technology" presented by Akito Yoshida

"Characterization of Intermetallic Compound (IMC) Growth in Cu Wire Ball Bonding on Al Pad Metallization" by SeokHo Na

Hope to see some of you next week in Orlando. For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edge……..

IFTLE 50 Words of Wisdom

50 is a big round number that means IFTLE is nearly a year old here on the SST website. From the data I’ve been shown recently, we have steadily built up readership since last spring to the point that we are now getting ~10,000 readers /month to this site. …….A sincere thank you for your interest.

As you know the Insights From the Leading Edge, or IFTLE as I like to call it, focuses on 3D integration and other advanced packaging technologies. We try to keep you abreast of where and when they are introduced and what kind of impact they will have on this field of Microelectronics that we have chosen to be a part of.

I just spent my 62nd birthday with my granddaughters in Houston. This gives me the opportunity to slip in another picture of the girls which I have already explained I get to do because this is my blog.

Miss Hanna (left) and Miss Madeline (right) informed me that 62 meant I was an old man. I told them that with age came experience and with experience came wisdom so they should listen to their old grandpa. They both just giggled not having a clue what I was talking about. Certainly we all get older, but do we all get wiser ? I’ll leave that as something for you to think about.

 

On my birthday I noticed that Dr Morris Chang had a few words to say in the China Post. Chang, Chairman and founder of TSMC and winner of the 2011 IEEE medal of honor, announced that TSMC is now capable of 28 nm and is focusing on 20 nm. He also announced that Moores Law would meet its demise by 2020 at which point we simply would not be shrinking transistors any more. These were strong words from a man who runs the worlds number one IC foundry. [Link] He pointed out that in the future, more attention will be paid on packaging solutions and printed wring boards which had not yet met their physical limits. For TSMC he pointed specifically to MEMS, image sensors, photovoltaics and LEDs.

At a TSMC forum April 5^th in Santa Clara Chang indicated that the PC and cell phones have been the big drivers for the IC industry but that now “ a third 'killer app. - mobile products (smart phones and tablets)” was ruling things.

Addressing 3D, Chang indicated that TSMC has poured "significant R and D" into 3-D chips using through-silicon vias (TSVs). The company calls it as a paradigm shift called "systems-level scaling," .

Looking at the 450 mm waer question he noted that "There are still a lot of challenges for 450-mm," and that TSMC “ would build a 450-mm pilot line in the 2013-2014 time frame, followed by production in 2015-2016” with “the intercept point is 20-nm”

Some might think that these concepts were put together by his underlings who are assigned to stay on top of technology, but maybe not. Chang has always been keenly interested in both the technology and the business aspects of our semiconductor industry since his early days at MIT.

My own experience with Dr Chang came about 12 years ago when I was in Taiwan introducing BCB for redistribution and bumping. We were visiting TSMC when our host informed us that the Chairman would be joining our meeting because he wanted to understand what all the of the interest in bumping and redistribution of chips was about. He personally took us out to lunch in order to have more time to absorb technical. He explained that he knew that bumping technology was being used by the mainframe players but had recently been hearing that it was moving into consumer products. A few years later, TSMC became the first foundry to put bumping capacity in place (2001). ……Morris Chang – without question is a wise, old man.

Intels new “3D technology”

As if we didn’t have enough trouble explaining that 3D IC technology has nothing to do with wearing glasses to watch your new TV, some reporters in the industry are now calling the Intel;tri gate transistor a “3D chip” [link] . Actually this is not something new, Intel first announced their tri-gate structure in September 2002 and indicated that they were readying it for introduction at 32 or 22 nm, which is exactly what they are doing.

This concept here is explained very nicely by Greg Crowe [link]. “Here’s the basic idea. A transistor has power flowing through it from the source end to the drain end. The presence or absence of a current is determined by the voltage level of the gate that bridges the two. The major problem with the traditional setup involves signal loss resulting from the fact that the gate only contacts the source and drain on one surface. A tri-gate transistor has three gates that make contact on three sides at once, effectively tripling the amount of surface through which electrons can travel. This produces less data leakage and uses less power than the older design.”

Intel has indicated that this will deliver a third more processing speed, and about half as much power consumption. This means that at 22 nm Intel can pack in twice as many transistors in about the same-sized chip for the same power usage, which operate a third faster – effectively giving us about 2.5X the processing power for the same power consumption.

There are those asking how this will affect the introduction of 3D IC. Only Intel knows for sure, but I can tell you that these faster ICs will be looking to access memory even faster than they do now so my guess would be that memory on logic will be needed even more.

My previous thoughts were that TSV would show up in the 22 nm Intel "ivy bridge" [see IFTLE 38, "..of Memory CUbes and Ivy Bridges..."] with both stacked memory and interposer. We will see whether that is still true.
So thanks for your continued readership and if you continue to be interesred in 3D IC integration and other advanced packaging, stay linked to IFTLE !

IFTLE 49 Mentor 3D-IC Test Strategy; GSA Memory Conf

Before we start this weeks topic, we have some corrections to offer up from IFTLE 48:

Semi and SEMATECH Lets Get it Straight

A SEMI representative got in touch to let me know that, while SEMI and some people from SEMATECH work together on 3D-IC standards, the two organizations do not have an alliance on TSV. “Both SEMI and SEMATECH are taking key leadership roles in the discussion and promotion of standards for 3D-IC technology. SEMATECH is working with SEMI on assembling standards committees and task forces. Working with SEMI, SEMATECH's goal is to leverage standards to head-off potential show-stoppers.”

“SEMI International Standards is very involved in 3D-IC manufacturing standards. The SEMI 3DS-IC Committee was created in late 2010, and has several activities underway in three task forces. The Inspection and Metrology Task Force is measuring the properties of TSVs, the Bonded Wafer Task Force is working on parameters for bonded wafer stacks, and the Thin Wafer Handling Task Force is developing standards for transport and storage. In addition, a new task force to address trimming of device wafers and carrier wafer dimensions is expected to start work at the 3DS-IC Committee’s next meeting on Tuesday, July 12, 2011 at SEMICON West 2011. The committee is currently chaired by Applied Materials, Qualcomm, Semilab, and SEMATECH. [link][link] and [link]

They also correctly noted that “3D Interconnect Wiki: Stress Management for TSVs” (http://wiki.sematech.org/ ) and the Wiki site (http://www.semiwiki.com/forum/f2/ ) are SEMATECH not SEMI sites.

Glad you all are paying attention, thanks for the corrections and I hope that straightens it all out.

Mentor Graphics 3D-IC Test Solution

Mentor Graphics Corporation recently announced their complete Mentor test solution for 3D-IC, Tessent® v9.4 which will be released May 2011 [link].

The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.

The Tessent test solution reportedly addresses the three main challenges of 3D-IC testing:
- the need for higher KGD test quality to ensure acceptable package yield
- the ability to enable comprehensive testing of all die within a packaged stack
- the ability to test all die interconnects after packaging

KGD is addressed by:

- Support for advanced fault models, including at speed testing in addition to normal “stuck-at” and bridge testing.
- Test pattern compression, which enables higher test coverage while lowering the cost of test by reducing tester memory requirements and test time.
- Hierarchical test capability, which simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips, limited by I/O pin count, routing congestion, or, in the case of 3D-ICs, inter die test paths
- Integration of automatic test pattern generation (ATPG) and built in self test (BIST) techniques to achieve highest coverage at the lowest cost.

3D-IC Test Challenges After Packaging

In 3D-IC stacks, each of the die must be re-tested after the die have been packaged to make sure they remain fully functional. Post-package test is the first opportunity to test all the TSV or interposer connections between die for proper connectivity and at-speed performance. For processor and memory stacks, the memory bus interface logic must also be tested at full speed.

Test point access is a problem because the bottom die is the only one with direct access pins. IMEC has proposed extensions to IEEE 1149.1 (which defines standard test access points0 to allow application of tests in multi-die stacks Their TSV-based 3D test architecture requires supporting methods for routing test data through the stack, and methods to re-sequence test patterns as appropriate for the extended scan chain paths. The Tessent tool suite provides support for implementing the IMEC extensions.

Tessent ATPG and BIST test products reportedly work together to minimize test development effort and to enable parallel testing to increase test throughput.

RAMBUS

At the GSA Memory Conference last month, Sharon Holt, Sr VP at Rambus reiterated the well known position that smartphone and tablet use is increasing and will overtake standard mobile phone use in 2015.

When looking at the options for mobile memory moving forward Holt proposes that the industry could continue to evolve todays technology based on low-power DDR2; switch to the newly announced wide I/O memory interface or use the Rambus designed XDR mobile memory solution.

 JEDEC has defined a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions. While Samsung and others have proposed commercialization in 2012 [see IFTLE 36, “RTI ASIP 2010 Part 2” ] and Nokia has indicated that they will see wide IO memory in production in 2013 [ see IFTLE 19, “Semicon Taiwan 3D Forum Part 2” ] Holt indicated that due to the complexity and costs, TSV-based wide I/O DRAM will probably not arrive until ''the second half of the decade’’.

SanDisk

Yoram Cedar, CTO of SanDisk took a look at flash memory.

Cedar expects to see a 5X increase in flash usage in the next 3 years :

Cedar concludes that NAND scaling will need new technologies in ~ 2014 and that “3D Read/Write Memory Will Likely Be the Successor to Floating Gate NAND Flash Over The Long Term” Note 3D here does not refer to TSV technology but rather as shown below.

Penn State

Yuan Xie, long time 3D practitioner from Penn State showed that 3D should have significant cost advantages over scaling at the 32 and 22 nodes.

What are the novel architectural designs enabled by 3D integration ?

- Latency (fast interlayer interconnect)

- Bandwidth (high number of connections bw layers)

- Heterogeneous integration

- Cost benefit

What “Killer” applications could benefit from the unique features 3D can bring ?

- High-capacity memory

- Multi/many-core ?

- Exascale computing ?

Kyowin Jin – Hynix Semiconductor

Kyowin Jin, VP of Product Planning for Hynix Semiconductor looked at the use of 3d technology in the DRAM industry. 3D TSV technology offers something to the computing, the graphics and the mobile segments of the memory industry.

Jin showed a Hynix 3D roadmap that shows prototype development for 3DS-RDIMM and for 3DS-DDR3 in 2-11 and ultra wide IO development in 2013 as shown below:

For all the latest in 3D IC and advanced packaging developments stay linked to Insights From the Leading Edge……………..